Add MLA instruction to ARM integerated assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 135e1b94dfcac5b582661747841a413e2e76433e..ad53d3f2d73436849bbd7878b877398a3bc6ee93 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -393,10 +393,9 @@ void AssemblerARM32::emitType01(IValueT Opcode, const Operand *OpRd,
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, RuleChecks);
 }
 
-void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd,
-                                IValueT Rn, const Operand *OpSrc1,
-                                bool SetFlags, CondARM32::Cond Cond,
-                                Type01Checks RuleChecks) {
+void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
+                                const Operand *OpSrc1, bool SetFlags,
+                                CondARM32::Cond Cond, Type01Checks RuleChecks) {
   switch (RuleChecks) {
   case NoChecks:
     break;
@@ -887,6 +886,35 @@ void AssemblerARM32::orr(const Operand *OpRd, const Operand *OpRn,
   emitType01(Orr, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
+void AssemblerARM32::mla(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpRm, const Operand *OpRa,
+                         CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rm;
+  if (decodeOperand(OpRm, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Ra;
+  if (decodeOperand(OpRa, Ra) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  // MLA - ARM section A8.8.114, encoding A1.
+  //   mla{s}<c> <Rd>, <Rn>, <Rm>, <Ra>
+  //
+  // cccc0000001sddddaaaammmm1001nnnn where cccc=Cond, s=SetFlags, dddd=Rd,
+  // aaaa=Ra, mmmm=Rm, and nnnn=Rn.
+  if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
+      Rm == RegARM32::Encoded_Reg_pc || Ra == RegARM32::Encoded_Reg_pc)
+    llvm::report_fatal_error("Mul instruction unpredictable on pc");
+  constexpr IValueT MlaOpcode = B21;
+  bool SetFlags = false;

[Jim Stichnoth, 2015/11/05 00:15:04]

constexpr

[Karl, 2015/11/05 16:28:20]

Done.

+  // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
+  emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, SetFlags);
+}
+
 void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {