Add MLA instruction to ARM integerated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 375 matching lines @@
                                 Type01Checks RuleChecks) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, RuleChecks);
 }
 
-void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd,
-                                IValueT Rn, const Operand *OpSrc1,
-                                bool SetFlags, CondARM32::Cond Cond,
-                                Type01Checks RuleChecks) {
+void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
+                                const Operand *OpSrc1, bool SetFlags,
+                                CondARM32::Cond Cond, Type01Checks RuleChecks) {
   switch (RuleChecks) {
   case NoChecks:
     break;
   case RdIsPcAndSetFlags:
     if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     break;
   }
 
@@ skipping 470 matching lines @@
   //
   // ORR (register) - ARM Section A8.8.123, encoding A1:
   //   orr{s}<c> <Rd>, <Rn>,  #<RotatedImm8>
   //
   // cccc0001100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Orr = B3 | B2; // i.e. 1100
   emitType01(Orr, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
+void AssemblerARM32::mla(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpRm, const Operand *OpRa,
+                         CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rm;
+  if (decodeOperand(OpRm, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Ra;
+  if (decodeOperand(OpRa, Ra) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  // MLA - ARM section A8.8.114, encoding A1.
+  //   mla{s}<c> <Rd>, <Rn>, <Rm>, <Ra>
+  //
+  // cccc0000001sddddaaaammmm1001nnnn where cccc=Cond, s=SetFlags, dddd=Rd,
+  // aaaa=Ra, mmmm=Rm, and nnnn=Rn.
+  if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
+      Rm == RegARM32::Encoded_Reg_pc || Ra == RegARM32::Encoded_Reg_pc)
+    llvm::report_fatal_error("Mul instruction unpredictable on pc");
+  constexpr IValueT MlaOpcode = B21;
+  bool SetFlags = false;

[Jim Stichnoth, 2015/11/05 00:15:04]

constexpr

[Karl, 2015/11/05 16:28:20]

Done.

+  // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
+  emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, SetFlags);
+}
+
 void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
@@ skipping 70 matching lines @@
   //   tst<c> <Rn>, #<RotatedImm8>
   //
   // cccc00110001nnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, and
   // iiiiiiiiiiii defines RotatedImm8.
   constexpr IValueT Opcode = B3; // ie. 1000
   emitCompareOp(Opcode, OpRn, OpSrc1, Cond);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice