Re-assign registers on ARM so PP and CODE_REG are below R7 (FP on iOS).

runtime/vm/constants_arm.h

Index: runtime/vm/constants_arm.h
diff --git a/runtime/vm/constants_arm.h b/runtime/vm/constants_arm.h
index 4a9ff3972892789d5ec63562ac92cc531286d143..51a6ebcb868d59789119555f2b1bc1e6f2b18cda 100644
--- a/runtime/vm/constants_arm.h
+++ b/runtime/vm/constants_arm.h
@@ -231,15 +231,15 @@ const FpuRegister kNoFpuRegister = kNoQRegister;
 // Register aliases.
 const Register TMP = IP;  // Used as scratch register by assembler.
 const Register TMP2 = kNoRegister;  // There is no second assembler temporary.
-const Register CTX = R10;  // Location of current context at method entry.
-const Register PP = R9;  // Caches object pool pointer in generated code.
+const Register CTX = R6;  // Location of current context at method entry.
+const Register PP = R5;  // Caches object pool pointer in generated code.
 const Register SPREG = SP;  // Stack pointer register.
 const Register FPREG = FP;  // Frame pointer register.
 const Register LRREG = LR;  // Link register.
-const Register ICREG = R5;  // IC data register.
+const Register ICREG = R9;  // IC data register.
 const Register ARGS_DESC_REG = R4;
-const Register CODE_REG = R10;
-const Register THR = R8;  // Caches current thread in generated code.
+const Register CODE_REG = R6;
+const Register THR = R10;  // Caches current thread in generated code.
 
 // R15 encodes APSR in the vmrs instruction.
 const Register APSR = R15;