Re-assign registers on ARM so PP and CODE_REG are below R7 (FP on iOS).

runtime/vm/disassembler_arm.cc

Index: runtime/vm/disassembler_arm.cc
diff --git a/runtime/vm/disassembler_arm.cc b/runtime/vm/disassembler_arm.cc
index 93ff293b4fae28bf7a388f29fb864c6d5c304875..26d535361a6776d4e46513799c441b613290f3af 100644
--- a/runtime/vm/disassembler_arm.cc
+++ b/runtime/vm/disassembler_arm.cc
@@ -109,11 +109,11 @@ void ARMDecoder::PrintCondition(Instr* instr) {
 
 
 // These register names are defined in a way to match the native disassembler
-// formatting, except for register alias pp (r9).
+// formatting, except for register alias pp (r5).
 // See for example the command "objdump -d <binary file>".
 static const char* reg_names[kNumberOfCpuRegisters] = {
-  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-  "r8", "pp", "r10", "fp", "ip", "sp", "lr", "pc",
+  "r0", "r1", "r2", "r3", "r4", "pp", "r6", "r7",
+  "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
 };