Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(506)

Issues Search
    My Issues | Starred     Open | Closed | All

Unified Diff: tests_lit/llvm2ice_tests/fp.cmp.ll

Issue 1417393003: Subzero. ARM32. New bool folding. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes lit tests. Created 5 years, 1 month ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« src/IceTargetLoweringARM32.cpp ('K') | « tests_lit/llvm2ice_tests/branch-opt.ll ('k') | tests_lit/llvm2ice_tests/select-opt.ll » ('j') | tests_lit/llvm2ice_tests/test_i1.ll » ('J')
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: tests_lit/llvm2ice_tests/fp.cmp.ll
diff --git a/tests_lit/llvm2ice_tests/fp.cmp.ll b/tests_lit/llvm2ice_tests/fp.cmp.ll
index 427a82c059901b15784eaaa964316d8836b49e29..0c0ae707f07f45465fd9995e95ede167aed6290a 100644
--- a/tests_lit/llvm2ice_tests/fp.cmp.ll
+++ b/tests_lit/llvm2ice_tests/fp.cmp.ll
@@ -52,13 +52,13 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-LABEL: fcmpEq
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32-OM1: movne [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: moveq [[R0]], #1
; ARM32-O2: bne
; ARM32: bl func
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32-OM1: movne [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
; ARM32-OM1: moveq [[R1]], #1
; ARM32-O2: bne
@@ -96,12 +96,12 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-LABEL: fcmpNe
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32-OM1: moveq [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: movne [[R0]], #1
; ARM32-O2: beq
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32-OM1: moveq [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
; ARM32-OM1: movne [[R1]], #1
; ARM32-O2: beq
@@ -135,12 +135,12 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-LABEL: fcmpGt
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32-OM1: movle [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: movgt [[R0]], #1
; ARM32-O2: ble
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32-OM1: movle [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
; ARM32-OM1: movgt [[R1]], #1
; ARM32-O2: ble
@@ -174,12 +174,12 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-LABEL: fcmpGe
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32-OM1: movge [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: movlt [[R0]], #1
; ARM32-O2: blt
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32-OM1: movge [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
; ARM32-OM1: movlt [[R1]], #1
; ARM32-O2: blt
@@ -213,12 +213,12 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-LABEL: fcmpLt
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32-OM1: movpl [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: movmi [[R0]], #1
; ARM32-O2: bpl
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32-OM1: movpl [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
; ARM32-OM1: movmi [[R1]], #1
; ARM32-O2: bpl
@@ -252,12 +252,12 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-LABEL: fcmpLe
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32-OM1: movls [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: movhi [[R0]], #1
; ARM32-O2: bhi
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32-OM1: movls [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
; ARM32-OM1: movhi [[R1]], #1
; ARM32-O2: bhi
@@ -294,9 +294,10 @@ entry:
; CHECK: jne
; CHECK: jp
; ARM32-LABEL: fcmpOeqFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movne [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: moveq [[R]], #1
define internal i32 @fcmpOeqDouble(double %a, double %b) {
@@ -310,9 +311,10 @@ entry:
; CHECK: jne
; CHECK: jp
; ARM32-LABEL: fcmpOeqDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movne [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: moveq [[R]], #1
define internal i32 @fcmpOgtFloat(float %a, float %b) {
@@ -325,9 +327,10 @@ entry:
; CHECK: ucomiss
; CHECK: seta
; ARM32-LABEL: fcmpOgtFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movle [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movgt [[R]], #1
define internal i32 @fcmpOgtDouble(double %a, double %b) {
@@ -340,9 +343,10 @@ entry:
; CHECK: ucomisd
; CHECK: seta
; ARM32-LABEL: fcmpOgtDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movle [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movgt [[R]], #1
define internal i32 @fcmpOgeFloat(float %a, float %b) {
@@ -355,9 +359,10 @@ entry:
; CHECK: ucomiss
; CHECK: setae
; ARM32-LABEL: fcmpOgeFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movlt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movge [[R]], #1
define internal i32 @fcmpOgeDouble(double %a, double %b) {
@@ -370,9 +375,10 @@ entry:
; CHECK: ucomisd
; CHECK: setae
; ARM32-LABEL: fcmpOgeDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movlt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movge [[R]], #1
define internal i32 @fcmpOltFloat(float %a, float %b) {
@@ -385,9 +391,10 @@ entry:
; CHECK: ucomiss
; CHECK: seta
; ARM32-LABEL: fcmpOltFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movpl [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movmi [[R]], #1
define internal i32 @fcmpOltDouble(double %a, double %b) {
@@ -400,9 +407,10 @@ entry:
; CHECK: ucomisd
; CHECK: seta
; ARM32-LABEL: fcmpOltDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movpl [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movmi [[R]], #1
define internal i32 @fcmpOleFloat(float %a, float %b) {
@@ -415,9 +423,10 @@ entry:
; CHECK: ucomiss
; CHECK: setae
; ARM32-LABEL: fcmpOleFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movhi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movls [[R]], #1
define internal i32 @fcmpOleDouble(double %a, double %b) {
@@ -430,9 +439,10 @@ entry:
; CHECK: ucomisd
; CHECK: setae
; ARM32-LABEL: fcmpOleDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movhi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movls [[R]], #1
define internal i32 @fcmpOneFloat(float %a, float %b) {
@@ -445,9 +455,10 @@ entry:
; CHECK: ucomiss
; CHECK: setne
; ARM32-LABEL: fcmpOneFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movmi [[R]], #1
; ARM32: movgt [[R]], #1
@@ -461,9 +472,10 @@ entry:
; CHECK: ucomisd
; CHECK: setne
; ARM32-LABEL: fcmpOneDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movmi [[R]], #1
; ARM32: movgt [[R]], #1
@@ -477,9 +489,10 @@ entry:
; CHECK: ucomiss
; CHECK: setnp
; ARM32-LABEL: fcmpOrdFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movvs [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movvc [[R]], #1
define internal i32 @fcmpOrdDouble(double %a, double %b) {
@@ -492,9 +505,10 @@ entry:
; CHECK: ucomisd
; CHECK: setnp
; ARM32-LABEL: fcmpOrdDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movvs [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movvc [[R]], #1
define internal i32 @fcmpUeqFloat(float %a, float %b) {
@@ -507,9 +521,10 @@ entry:
; CHECK: ucomiss
; CHECK: sete
; ARM32-LABEL: fcmpUeqFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: moveq [[R]], #1
; ARM32: movvs [[R]], #1
@@ -523,9 +538,10 @@ entry:
; CHECK: ucomisd
; CHECK: sete
; ARM32-LABEL: fcmpUeqDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: moveq [[R]], #1
; ARM32: movvs [[R]], #1
@@ -539,9 +555,10 @@ entry:
; CHECK: ucomiss
; CHECK: setb
; ARM32-LABEL: fcmpUgtFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movls [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movhi [[R]], #1
define internal i32 @fcmpUgtDouble(double %a, double %b) {
@@ -554,9 +571,10 @@ entry:
; CHECK: ucomisd
; CHECK: setb
; ARM32-LABEL: fcmpUgtDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movls [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movhi [[R]], #1
define internal i32 @fcmpUgeFloat(float %a, float %b) {
@@ -569,9 +587,10 @@ entry:
; CHECK: ucomiss
; CHECK: setbe
; ARM32-LABEL: fcmpUgeFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movmi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movpl [[R]], #1
define internal i32 @fcmpUgeDouble(double %a, double %b) {
@@ -584,9 +603,10 @@ entry:
; CHECK: ucomisd
; CHECK: setbe
; ARM32-LABEL: fcmpUgeDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movmi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movpl [[R]], #1
define internal i32 @fcmpUltFloat(float %a, float %b) {
@@ -599,9 +619,10 @@ entry:
; CHECK: ucomiss
; CHECK: setb
; ARM32-LABEL: fcmpUltFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movge [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movlt [[R]], #1
define internal i32 @fcmpUltDouble(double %a, double %b) {
@@ -614,9 +635,10 @@ entry:
; CHECK: ucomisd
; CHECK: setb
; ARM32-LABEL: fcmpUltDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movge [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movlt [[R]], #1
define internal i32 @fcmpUleFloat(float %a, float %b) {
@@ -629,9 +651,10 @@ entry:
; CHECK: ucomiss
; CHECK: setbe
; ARM32-LABEL: fcmpUleFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movgt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movle [[R]], #1
define internal i32 @fcmpUleDouble(double %a, double %b) {
@@ -644,9 +667,10 @@ entry:
; CHECK: ucomisd
; CHECK: setbe
; ARM32-LABEL: fcmpUleDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movgt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movle [[R]], #1
define internal i32 @fcmpUneFloat(float %a, float %b) {
@@ -660,9 +684,10 @@ entry:
; CHECK: jne
; CHECK: jp
; ARM32-LABEL: fcmpUneFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: moveq [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movne [[R]], #1
define internal i32 @fcmpUneDouble(double %a, double %b) {
@@ -676,9 +701,10 @@ entry:
; CHECK: jne
; CHECK: jp
; ARM32-LABEL: fcmpUneDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: moveq [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movne [[R]], #1
define internal i32 @fcmpUnoFloat(float %a, float %b) {
@@ -691,9 +717,10 @@ entry:
; CHECK: ucomiss
; CHECK: setp
; ARM32-LABEL: fcmpUnoFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f32
; ARM32: vmrs
-; ARM32: movvc [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movvs [[R]], #1
define internal i32 @fcmpUnoDouble(double %a, double %b) {
@@ -706,9 +733,10 @@ entry:
; CHECK: ucomisd
; CHECK: setp
; ARM32-LABEL: fcmpUnoDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
; ARM32: vcmp.f64
; ARM32: vmrs
-; ARM32: movvc [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
; ARM32: movvs [[R]], #1
define internal i32 @fcmpTrueFloat(float %a, float %b) {
« src/IceTargetLoweringARM32.cpp ('K') | « tests_lit/llvm2ice_tests/branch-opt.ll ('k') | tests_lit/llvm2ice_tests/select-opt.ll » ('j') | tests_lit/llvm2ice_tests/test_i1.ll » ('J')

Powered by Google App Engine
This is Rietveld 408576698