Subzero. ARM32. New bool folding.

tests_lit/llvm2ice_tests/fp.cmp.ll

 ; This tries to be a comprehensive test of f32 and f64 compare operations.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 34 matching lines @@
 ; CHECK: jne
 ; CHECK-NEXT: jp
 ; CHECK: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
 ; CHECK: jne
 ; CHECK-NEXT: jp
 ; CHECK: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpEq
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32-OM1: movne [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
 ; ARM32-OM1: moveq [[R0]], #1
 ; ARM32-O2: bne
 ; ARM32: bl func
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32-OM1: movne [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
 ; ARM32-OM1: moveq [[R1]], #1
 ; ARM32-O2: bne
 
 declare void @func()
 
 define internal void @fcmpNe(float %a, float %b, double %c, double %d) {
 entry:
   %cmp = fcmp une float %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
@@ skipping 17 matching lines @@
 ; CHECK: jne
 ; CHECK-NEXT: jp
 ; CHECK: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
 ; CHECK: jne
 ; CHECK-NEXT: jp
 ; CHECK: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpNe
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32-OM1: moveq [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movne [[R0]], #1
 ; ARM32-O2: beq
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32-OM1: moveq [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movne [[R1]], #1
 ; ARM32-O2: beq
 
 define internal void @fcmpGt(float %a, float %b, double %c, double %d) {
 entry:
   %cmp = fcmp ogt float %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
@@ skipping 13 matching lines @@
 ; CHECK-LABEL: fcmpGt
 ; CHECK: ucomiss
 ; CHECK: seta
 ; CHECK: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
 ; CHECK: seta
 ; CHECK: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpGt
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32-OM1: movle [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movgt [[R0]], #1
 ; ARM32-O2: ble
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32-OM1: movle [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movgt [[R1]], #1
 ; ARM32-O2: ble
 
 define internal void @fcmpGe(float %a, float %b, double %c, double %d) {
 entry:
   %cmp = fcmp ult float %a, %b
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
   call void @func()
@@ skipping 13 matching lines @@
 ; CHECK-LABEL: fcmpGe
 ; CHECK: ucomiss
 ; CHECK: setb
 ; CHECK: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
 ; CHECK: setb
 ; CHECK: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpGe
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32-OM1: movge [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movlt [[R0]], #1
 ; ARM32-O2: blt
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32-OM1: movge [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movlt [[R1]], #1
 ; ARM32-O2: blt
 
 define internal void @fcmpLt(float %a, float %b, double %c, double %d) {
 entry:
   %cmp = fcmp olt float %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
@@ skipping 13 matching lines @@
 ; CHECK-LABEL: fcmpLt
 ; CHECK: ucomiss
 ; CHECK: seta
 ; CHECK: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
 ; CHECK: seta
 ; CHECK: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpLt
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32-OM1: movpl [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movmi [[R0]], #1
 ; ARM32-O2: bpl
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32-OM1: movpl [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movmi [[R1]], #1
 ; ARM32-O2: bpl
 
 define internal void @fcmpLe(float %a, float %b, double %c, double %d) {
 entry:
   %cmp = fcmp ugt float %a, %b
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
   call void @func()
@@ skipping 13 matching lines @@
 ; CHECK-LABEL: fcmpLe
 ; CHECK: ucomiss
 ; CHECK: setb
 ; CHECK: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
 ; CHECK: setb
 ; CHECK: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpLe
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32-OM1: movls [[R0:r[0-9]+]], #0
+; ARM32-OM1: mov [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movhi [[R0]], #1
 ; ARM32-O2: bhi
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32-OM1: movls [[R1:r[0-9]+]], #0
+; ARM32-OM1: mov [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movhi [[R1]], #1
 ; ARM32-O2: bhi
 
 define internal i32 @fcmpFalseFloat(float %a, float %b) {
 entry:
   %cmp = fcmp false float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpFalseFloat
@@ skipping 16 matching lines @@
 entry:
   %cmp = fcmp oeq float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOeqFloat
 ; CHECK: ucomiss
 ; CHECK: jne
 ; CHECK: jp
 ; ARM32-LABEL: fcmpOeqFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movne [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: moveq [[R]], #1
 
 define internal i32 @fcmpOeqDouble(double %a, double %b) {
 entry:
   %cmp = fcmp oeq double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOeqDouble
 ; CHECK: ucomisd
 ; CHECK: jne
 ; CHECK: jp
 ; ARM32-LABEL: fcmpOeqDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movne [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: moveq [[R]], #1
 
 define internal i32 @fcmpOgtFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ogt float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOgtFloat
 ; CHECK: ucomiss
 ; CHECK: seta
 ; ARM32-LABEL: fcmpOgtFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movle [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movgt [[R]], #1
 
 define internal i32 @fcmpOgtDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ogt double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOgtDouble
 ; CHECK: ucomisd
 ; CHECK: seta
 ; ARM32-LABEL: fcmpOgtDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movle [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movgt [[R]], #1
 
 define internal i32 @fcmpOgeFloat(float %a, float %b) {
 entry:
   %cmp = fcmp oge float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOgeFloat
 ; CHECK: ucomiss
 ; CHECK: setae
 ; ARM32-LABEL: fcmpOgeFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movlt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movge [[R]], #1
 
 define internal i32 @fcmpOgeDouble(double %a, double %b) {
 entry:
   %cmp = fcmp oge double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOgeDouble
 ; CHECK: ucomisd
 ; CHECK: setae
 ; ARM32-LABEL: fcmpOgeDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movlt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movge [[R]], #1
 
 define internal i32 @fcmpOltFloat(float %a, float %b) {
 entry:
   %cmp = fcmp olt float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOltFloat
 ; CHECK: ucomiss
 ; CHECK: seta
 ; ARM32-LABEL: fcmpOltFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movpl [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movmi [[R]], #1
 
 define internal i32 @fcmpOltDouble(double %a, double %b) {
 entry:
   %cmp = fcmp olt double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOltDouble
 ; CHECK: ucomisd
 ; CHECK: seta
 ; ARM32-LABEL: fcmpOltDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movpl [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movmi [[R]], #1
 
 define internal i32 @fcmpOleFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ole float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOleFloat
 ; CHECK: ucomiss
 ; CHECK: setae
 ; ARM32-LABEL: fcmpOleFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movhi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movls [[R]], #1
 
 define internal i32 @fcmpOleDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ole double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOleDouble
 ; CHECK: ucomisd
 ; CHECK: setae
 ; ARM32-LABEL: fcmpOleDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movhi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movls [[R]], #1
 
 define internal i32 @fcmpOneFloat(float %a, float %b) {
 entry:
   %cmp = fcmp one float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOneFloat
 ; CHECK: ucomiss
 ; CHECK: setne
 ; ARM32-LABEL: fcmpOneFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movmi [[R]], #1
 ; ARM32: movgt [[R]], #1
 
 define internal i32 @fcmpOneDouble(double %a, double %b) {
 entry:
   %cmp = fcmp one double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOneDouble
 ; CHECK: ucomisd
 ; CHECK: setne
 ; ARM32-LABEL: fcmpOneDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movmi [[R]], #1
 ; ARM32: movgt [[R]], #1
 
 define internal i32 @fcmpOrdFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ord float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOrdFloat
 ; CHECK: ucomiss
 ; CHECK: setnp
 ; ARM32-LABEL: fcmpOrdFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movvs [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movvc [[R]], #1
 
 define internal i32 @fcmpOrdDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ord double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpOrdDouble
 ; CHECK: ucomisd
 ; CHECK: setnp
 ; ARM32-LABEL: fcmpOrdDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movvs [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movvc [[R]], #1
 
 define internal i32 @fcmpUeqFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ueq float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUeqFloat
 ; CHECK: ucomiss
 ; CHECK: sete
 ; ARM32-LABEL: fcmpUeqFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: moveq [[R]], #1
 ; ARM32: movvs [[R]], #1
 
 define internal i32 @fcmpUeqDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ueq double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUeqDouble
 ; CHECK: ucomisd
 ; CHECK: sete
 ; ARM32-LABEL: fcmpUeqDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: mov [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: moveq [[R]], #1
 ; ARM32: movvs [[R]], #1
 
 define internal i32 @fcmpUgtFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ugt float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUgtFloat
 ; CHECK: ucomiss
 ; CHECK: setb
 ; ARM32-LABEL: fcmpUgtFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movls [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movhi [[R]], #1
 
 define internal i32 @fcmpUgtDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ugt double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUgtDouble
 ; CHECK: ucomisd
 ; CHECK: setb
 ; ARM32-LABEL: fcmpUgtDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movls [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movhi [[R]], #1
 
 define internal i32 @fcmpUgeFloat(float %a, float %b) {
 entry:
   %cmp = fcmp uge float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUgeFloat
 ; CHECK: ucomiss
 ; CHECK: setbe
 ; ARM32-LABEL: fcmpUgeFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movmi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movpl [[R]], #1
 
 define internal i32 @fcmpUgeDouble(double %a, double %b) {
 entry:
   %cmp = fcmp uge double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUgeDouble
 ; CHECK: ucomisd
 ; CHECK: setbe
 ; ARM32-LABEL: fcmpUgeDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movmi [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movpl [[R]], #1
 
 define internal i32 @fcmpUltFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ult float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUltFloat
 ; CHECK: ucomiss
 ; CHECK: setb
 ; ARM32-LABEL: fcmpUltFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movge [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movlt [[R]], #1
 
 define internal i32 @fcmpUltDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ult double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUltDouble
 ; CHECK: ucomisd
 ; CHECK: setb
 ; ARM32-LABEL: fcmpUltDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movge [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movlt [[R]], #1
 
 define internal i32 @fcmpUleFloat(float %a, float %b) {
 entry:
   %cmp = fcmp ule float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUleFloat
 ; CHECK: ucomiss
 ; CHECK: setbe
 ; ARM32-LABEL: fcmpUleFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movgt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movle [[R]], #1
 
 define internal i32 @fcmpUleDouble(double %a, double %b) {
 entry:
   %cmp = fcmp ule double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUleDouble
 ; CHECK: ucomisd
 ; CHECK: setbe
 ; ARM32-LABEL: fcmpUleDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movgt [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movle [[R]], #1
 
 define internal i32 @fcmpUneFloat(float %a, float %b) {
 entry:
   %cmp = fcmp une float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUneFloat
 ; CHECK: ucomiss
 ; CHECK: jne
 ; CHECK: jp
 ; ARM32-LABEL: fcmpUneFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: moveq [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movne [[R]], #1
 
 define internal i32 @fcmpUneDouble(double %a, double %b) {
 entry:
   %cmp = fcmp une double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUneDouble
 ; CHECK: ucomisd
 ; CHECK: jne
 ; CHECK: jp
 ; ARM32-LABEL: fcmpUneDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: moveq [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movne [[R]], #1
 
 define internal i32 @fcmpUnoFloat(float %a, float %b) {
 entry:
   %cmp = fcmp uno float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUnoFloat
 ; CHECK: ucomiss
 ; CHECK: setp
 ; ARM32-LABEL: fcmpUnoFloat
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
-; ARM32: movvc [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movvs [[R]], #1
 
 define internal i32 @fcmpUnoDouble(double %a, double %b) {
 entry:
   %cmp = fcmp uno double %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpUnoDouble
 ; CHECK: ucomisd
 ; CHECK: setp
 ; ARM32-LABEL: fcmpUnoDouble
+; ARM32-O2: mov [[R:r[0-9]+]], #0
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
-; ARM32: movvc [[R:r[0-9]+]], #0
+; ARM32-OM1: mov [[R:r[0-9]+]], #0
 ; ARM32: movvs [[R]], #1
 
 define internal i32 @fcmpTrueFloat(float %a, float %b) {
 entry:
   %cmp = fcmp true float %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: fcmpTrueFloat
 ; CHECK: mov {{.*}},0x1
@@ skipping 35 matching lines @@
 }
 ; CHECK-LABEL: selectDoubleVarVar
 ; CHECK: ucomisd
 ; CHECK: seta
 ; CHECK: fld
 ; ARM32-LABEL: selectDoubleVarVar
 ; ARM32: vcmp.f64
 ; ARM32-OM1: vmovne.f64 d{{[0-9]+}}
 ; ARM32-O2: vmovmi.f64 d{{[0-9]+}}
 ; ARM32: bx