| Index: tests_lit/llvm2ice_tests/vector-select.ll
|
| diff --git a/tests_lit/llvm2ice_tests/vector-select.ll b/tests_lit/llvm2ice_tests/vector-select.ll
|
| index 4ce8f382179fb6cd0ac7e24238dac0a5d985132a..6e08d3ffcb7cea37b4632b435dd340626950efe8 100644
|
| --- a/tests_lit/llvm2ice_tests/vector-select.ll
|
| +++ b/tests_lit/llvm2ice_tests/vector-select.ll
|
| @@ -9,7 +9,8 @@
|
| ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
|
| ; RUN: | FileCheck --check-prefix=SSE41 %s
|
|
|
| -define <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2) {
|
| +define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1,
|
| + <16 x i8> %arg2) {
|
| entry:
|
| %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2
|
| ret <16 x i8> %res
|
| @@ -22,7 +23,8 @@ entry:
|
| ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
|
| }
|
|
|
| -define <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2) {
|
| +define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1,
|
| + <16 x i1> %arg2) {
|
| entry:
|
| %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2
|
| ret <16 x i1> %res
|
| @@ -35,7 +37,8 @@ entry:
|
| ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
|
| }
|
|
|
| -define <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2) {
|
| +define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1,
|
| + <8 x i16> %arg2) {
|
| entry:
|
| %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2
|
| ret <8 x i16> %res
|
| @@ -48,7 +51,8 @@ entry:
|
| ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
|
| }
|
|
|
| -define <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2) {
|
| +define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1,
|
| + <8 x i1> %arg2) {
|
| entry:
|
| %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
|
| ret <8 x i1> %res
|
| @@ -61,7 +65,8 @@ entry:
|
| ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
|
| }
|
|
|
| -define <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2) {
|
| +define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1,
|
| + <4 x i32> %arg2) {
|
| entry:
|
| %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2
|
| ret <4 x i32> %res
|
| @@ -75,7 +80,8 @@ entry:
|
| ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
|
| }
|
|
|
| -define <4 x float> @test_select_v4f32(<4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) {
|
| +define internal <4 x float> @test_select_v4f32(
|
| + <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) {
|
| entry:
|
| %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2
|
| ret <4 x float> %res
|
| @@ -89,7 +95,8 @@ entry:
|
| ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
|
| }
|
|
|
| -define <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2) {
|
| +define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1,
|
| + <4 x i1> %arg2) {
|
| entry:
|
| %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2
|
| ret <4 x i1> %res
|
|
|