| OLD | NEW |
| 1 ; This file tests support for the select instruction with vector valued inputs. | 1 ; This file tests support for the select instruction with vector valued inputs. |
| 2 | 2 |
| 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ | 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ |
| 4 ; RUN: | FileCheck %s | 4 ; RUN: | FileCheck %s |
| 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ | 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ |
| 6 ; RUN: | FileCheck %s | 6 ; RUN: | FileCheck %s |
| 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ | 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ |
| 8 ; RUN: | FileCheck --check-prefix=SSE41 %s | 8 ; RUN: | FileCheck --check-prefix=SSE41 %s |
| 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ | 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ |
| 10 ; RUN: | FileCheck --check-prefix=SSE41 %s | 10 ; RUN: | FileCheck --check-prefix=SSE41 %s |
| 11 | 11 |
| 12 define <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, <16 x i8>
%arg2) { | 12 define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, |
| 13 <16 x i8> %arg2) { |
| 13 entry: | 14 entry: |
| 14 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 | 15 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 |
| 15 ret <16 x i8> %res | 16 ret <16 x i8> %res |
| 16 ; CHECK-LABEL: test_select_v16i8 | 17 ; CHECK-LABEL: test_select_v16i8 |
| 17 ; CHECK: pand | 18 ; CHECK: pand |
| 18 ; CHECK: pandn | 19 ; CHECK: pandn |
| 19 ; CHECK: por | 20 ; CHECK: por |
| 20 | 21 |
| 21 ; SSE41-LABEL: test_select_v16i8 | 22 ; SSE41-LABEL: test_select_v16i8 |
| 22 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 23 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 23 } | 24 } |
| 24 | 25 |
| 25 define <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, <16 x i1>
%arg2) { | 26 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, |
| 27 <16 x i1> %arg2) { |
| 26 entry: | 28 entry: |
| 27 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 | 29 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 |
| 28 ret <16 x i1> %res | 30 ret <16 x i1> %res |
| 29 ; CHECK-LABEL: test_select_v16i1 | 31 ; CHECK-LABEL: test_select_v16i1 |
| 30 ; CHECK: pand | 32 ; CHECK: pand |
| 31 ; CHECK: pandn | 33 ; CHECK: pandn |
| 32 ; CHECK: por | 34 ; CHECK: por |
| 33 | 35 |
| 34 ; SSE41-LABEL: test_select_v16i1 | 36 ; SSE41-LABEL: test_select_v16i1 |
| 35 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 37 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 36 } | 38 } |
| 37 | 39 |
| 38 define <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %
arg2) { | 40 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, |
| 41 <8 x i16> %arg2) { |
| 39 entry: | 42 entry: |
| 40 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 | 43 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 |
| 41 ret <8 x i16> %res | 44 ret <8 x i16> %res |
| 42 ; CHECK-LABEL: test_select_v8i16 | 45 ; CHECK-LABEL: test_select_v8i16 |
| 43 ; CHECK: pand | 46 ; CHECK: pand |
| 44 ; CHECK: pandn | 47 ; CHECK: pandn |
| 45 ; CHECK: por | 48 ; CHECK: por |
| 46 | 49 |
| 47 ; SSE41-LABEL: test_select_v8i16 | 50 ; SSE41-LABEL: test_select_v8i16 |
| 48 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 51 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 49 } | 52 } |
| 50 | 53 |
| 51 define <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
) { | 54 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, |
| 55 <8 x i1> %arg2) { |
| 52 entry: | 56 entry: |
| 53 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 | 57 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 |
| 54 ret <8 x i1> %res | 58 ret <8 x i1> %res |
| 55 ; CHECK-LABEL: test_select_v8i1 | 59 ; CHECK-LABEL: test_select_v8i1 |
| 56 ; CHECK: pand | 60 ; CHECK: pand |
| 57 ; CHECK: pandn | 61 ; CHECK: pandn |
| 58 ; CHECK: por | 62 ; CHECK: por |
| 59 | 63 |
| 60 ; SSE41-LABEL: test_select_v8i1 | 64 ; SSE41-LABEL: test_select_v8i1 |
| 61 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 65 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 62 } | 66 } |
| 63 | 67 |
| 64 define <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %
arg2) { | 68 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, |
| 69 <4 x i32> %arg2) { |
| 65 entry: | 70 entry: |
| 66 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 | 71 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 |
| 67 ret <4 x i32> %res | 72 ret <4 x i32> %res |
| 68 ; CHECK-LABEL: test_select_v4i32 | 73 ; CHECK-LABEL: test_select_v4i32 |
| 69 ; CHECK: pand | 74 ; CHECK: pand |
| 70 ; CHECK: pandn | 75 ; CHECK: pandn |
| 71 ; CHECK: por | 76 ; CHECK: por |
| 72 | 77 |
| 73 ; SSE41-LABEL: test_select_v4i32 | 78 ; SSE41-LABEL: test_select_v4i32 |
| 74 ; SSE41: pslld xmm0,0x1f | 79 ; SSE41: pslld xmm0,0x1f |
| 75 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 80 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 76 } | 81 } |
| 77 | 82 |
| 78 define <4 x float> @test_select_v4f32(<4 x i1> %cond, <4 x float> %arg1, <4 x fl
oat> %arg2) { | 83 define internal <4 x float> @test_select_v4f32( |
| 84 <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) { |
| 79 entry: | 85 entry: |
| 80 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 | 86 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 |
| 81 ret <4 x float> %res | 87 ret <4 x float> %res |
| 82 ; CHECK-LABEL: test_select_v4f32 | 88 ; CHECK-LABEL: test_select_v4f32 |
| 83 ; CHECK: pand | 89 ; CHECK: pand |
| 84 ; CHECK: pandn | 90 ; CHECK: pandn |
| 85 ; CHECK: por | 91 ; CHECK: por |
| 86 | 92 |
| 87 ; SSE41-LABEL: test_select_v4f32 | 93 ; SSE41-LABEL: test_select_v4f32 |
| 88 ; SSE41: pslld xmm0,0x1f | 94 ; SSE41: pslld xmm0,0x1f |
| 89 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 95 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 90 } | 96 } |
| 91 | 97 |
| 92 define <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2
) { | 98 define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, |
| 99 <4 x i1> %arg2) { |
| 93 entry: | 100 entry: |
| 94 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 | 101 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 |
| 95 ret <4 x i1> %res | 102 ret <4 x i1> %res |
| 96 ; CHECK-LABEL: test_select_v4i1 | 103 ; CHECK-LABEL: test_select_v4i1 |
| 97 ; CHECK: pand | 104 ; CHECK: pand |
| 98 ; CHECK: pandn | 105 ; CHECK: pandn |
| 99 ; CHECK: por | 106 ; CHECK: por |
| 100 | 107 |
| 101 ; SSE41-LABEL: test_select_v4i1 | 108 ; SSE41-LABEL: test_select_v4i1 |
| 102 ; SSE41: pslld xmm0,0x1f | 109 ; SSE41: pslld xmm0,0x1f |
| 103 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 110 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 104 } | 111 } |
| OLD | NEW |