Index: tests_lit/llvm2ice_tests/vector-cast.ll |
diff --git a/tests_lit/llvm2ice_tests/vector-cast.ll b/tests_lit/llvm2ice_tests/vector-cast.ll |
index 3dae1fc7bc6352cb124c4848dffbfe81dcd23226..d36b7b9e924cb542bab1009cd313fd7f50e25c94 100644 |
--- a/tests_lit/llvm2ice_tests/vector-cast.ll |
+++ b/tests_lit/llvm2ice_tests/vector-cast.ll |
@@ -6,7 +6,7 @@ |
; sext operations |
-define <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) { |
+define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) { |
entry: |
%res = sext <16 x i1> %arg to <16 x i8> |
ret <16 x i8> %res |
@@ -20,7 +20,7 @@ entry: |
; CHECK: pcmpgtb |
} |
-define <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) { |
+define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) { |
entry: |
%res = sext <8 x i1> %arg to <8 x i16> |
ret <8 x i16> %res |
@@ -30,7 +30,7 @@ entry: |
; CHECK: psraw {{.*}},0xf |
} |
-define <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) { |
+define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) { |
entry: |
%res = sext <4 x i1> %arg to <4 x i32> |
ret <4 x i32> %res |
@@ -42,7 +42,7 @@ entry: |
; zext operations |
-define <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) { |
+define internal <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) { |
entry: |
%res = zext <16 x i1> %arg to <16 x i8> |
ret <16 x i8> %res |
@@ -54,7 +54,7 @@ entry: |
; CHECK: pand |
} |
-define <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) { |
+define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) { |
entry: |
%res = zext <8 x i1> %arg to <8 x i16> |
ret <8 x i16> %res |
@@ -66,7 +66,7 @@ entry: |
; CHECK: pand |
} |
-define <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) { |
+define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) { |
entry: |
%res = zext <4 x i1> %arg to <4 x i32> |
ret <4 x i32> %res |
@@ -80,7 +80,7 @@ entry: |
; trunc operations |
-define <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) { |
+define internal <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) { |
entry: |
%res = trunc <16 x i8> %arg to <16 x i1> |
ret <16 x i1> %res |
@@ -92,7 +92,7 @@ entry: |
; CHECK: pand |
} |
-define <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) { |
+define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) { |
entry: |
%res = trunc <8 x i16> %arg to <8 x i1> |
ret <8 x i1> %res |
@@ -104,7 +104,7 @@ entry: |
; CHECK: pand |
} |
-define <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) { |
+define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) { |
entry: |
%res = trunc <4 x i32> %arg to <4 x i1> |
ret <4 x i1> %res |
@@ -118,7 +118,7 @@ entry: |
; fpto[us]i operations |
-define <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) { |
+define internal <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) { |
entry: |
%res = fptosi <4 x float> %arg to <4 x i32> |
ret <4 x i32> %res |
@@ -127,7 +127,7 @@ entry: |
; CHECK: cvttps2dq |
} |
-define <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) { |
+define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) { |
entry: |
%res = fptoui <4 x float> %arg to <4 x i32> |
ret <4 x i32> %res |
@@ -138,7 +138,7 @@ entry: |
; [su]itofp operations |
-define <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) { |
+define internal <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) { |
entry: |
%res = sitofp <4 x i32> %arg to <4 x float> |
ret <4 x float> %res |
@@ -147,7 +147,7 @@ entry: |
; CHECK: cvtdq2ps |
} |
-define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { |
+define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { |
entry: |
%res = uitofp <4 x i32> %arg to <4 x float> |
ret <4 x float> %res |