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Unified Diff: src/mips/assembler-mips.cc

Issue 1365073002: Revert of Remove register index/code indirection (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 3 months ago
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Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index 87abbe1b4d1ea6ba01a2d7f697d5042baa7bb73c..7fa4d5d66a5c2fe2c97f67c480811c189c6e99d0 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -61,6 +61,28 @@
#endif
return answer;
+}
+
+
+const char* DoubleRegister::AllocationIndexToString(int index) {
+ DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
+ const char* const names[] = {
+ "f0",
+ "f2",
+ "f4",
+ "f6",
+ "f8",
+ "f10",
+ "f12",
+ "f14",
+ "f16",
+ "f18",
+ "f20",
+ "f22",
+ "f24",
+ "f26"
+ };
+ return names[index];
}
@@ -228,31 +250,31 @@
static const int kNegOffset = 0x00008000;
// addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
// operations as post-increment of sp.
-const Instr kPopInstruction = ADDIU | (Register::kCode_sp << kRsShift) |
- (Register::kCode_sp << kRtShift) |
- (kPointerSize & kImm16Mask); // NOLINT
+const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
+ | (kRegister_sp_Code << kRtShift)
+ | (kPointerSize & kImm16Mask); // NOLINT
// addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
-const Instr kPushInstruction = ADDIU | (Register::kCode_sp << kRsShift) |
- (Register::kCode_sp << kRtShift) |
- (-kPointerSize & kImm16Mask); // NOLINT
+const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
+ | (kRegister_sp_Code << kRtShift)
+ | (-kPointerSize & kImm16Mask); // NOLINT
// sw(r, MemOperand(sp, 0))
-const Instr kPushRegPattern =
- SW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT
+const Instr kPushRegPattern = SW | (kRegister_sp_Code << kRsShift)
+ | (0 & kImm16Mask); // NOLINT
// lw(r, MemOperand(sp, 0))
-const Instr kPopRegPattern =
- LW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT
-
-const Instr kLwRegFpOffsetPattern =
- LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
-
-const Instr kSwRegFpOffsetPattern =
- SW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
-
-const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
- (kNegOffset & kImm16Mask); // NOLINT
-
-const Instr kSwRegFpNegOffsetPattern = SW | (Register::kCode_fp << kRsShift) |
- (kNegOffset & kImm16Mask); // NOLINT
+const Instr kPopRegPattern = LW | (kRegister_sp_Code << kRsShift)
+ | (0 & kImm16Mask); // NOLINT
+
+const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
+ | (0 & kImm16Mask); // NOLINT
+
+const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
+ | (0 & kImm16Mask); // NOLINT
+
+const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
+ | (kNegOffset & kImm16Mask); // NOLINT
+
+const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
+ | (kNegOffset & kImm16Mask); // NOLINT
// A mask for the Rt register for push, pop, lw, sw instructions.
const Instr kRtMask = kRtFieldMask;
const Instr kLwSwInstrTypeMask = 0xffe00000;
@@ -312,21 +334,21 @@
Register Assembler::GetRtReg(Instr instr) {
Register rt;
- rt.reg_code = (instr & kRtFieldMask) >> kRtShift;
+ rt.code_ = (instr & kRtFieldMask) >> kRtShift;
return rt;
}
Register Assembler::GetRsReg(Instr instr) {
Register rs;
- rs.reg_code = (instr & kRsFieldMask) >> kRsShift;
+ rs.code_ = (instr & kRsFieldMask) >> kRsShift;
return rs;
}
Register Assembler::GetRdReg(Instr instr) {
Register rd;
- rd.reg_code = (instr & kRdFieldMask) >> kRdShift;
+ rd.code_ = (instr & kRdFieldMask) >> kRdShift;
return rd;
}
@@ -1920,14 +1942,14 @@
void Assembler::movt(Register rd, Register rs, uint16_t cc) {
Register rt;
- rt.reg_code = (cc & 0x0007) << 2 | 1;
+ rt.code_ = (cc & 0x0007) << 2 | 1;
GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
}
void Assembler::movf(Register rd, Register rs, uint16_t cc) {
Register rt;
- rt.reg_code = (cc & 0x0007) << 2 | 0;
+ rt.code_ = (cc & 0x0007) << 2 | 0;
GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
}
@@ -2211,7 +2233,7 @@
void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
DCHECK(IsMipsArchVariant(kMips32r2));
FPURegister ft;
- ft.reg_code = (cc & 0x0007) << 2 | 1;
+ ft.code_ = (cc & 0x0007) << 2 | 1;
GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
}
@@ -2219,7 +2241,7 @@
void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
DCHECK(IsMipsArchVariant(kMips32r2));
FPURegister ft;
- ft.reg_code = (cc & 0x0007) << 2 | 1;
+ ft.code_ = (cc & 0x0007) << 2 | 1;
GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
}
@@ -2227,7 +2249,7 @@
void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
DCHECK(IsMipsArchVariant(kMips32r2));
FPURegister ft;
- ft.reg_code = (cc & 0x0007) << 2 | 0;
+ ft.code_ = (cc & 0x0007) << 2 | 0;
GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
}
@@ -2235,7 +2257,7 @@
void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) {
DCHECK(IsMipsArchVariant(kMips32r2));
FPURegister ft;
- ft.reg_code = (cc & 0x0007) << 2 | 0;
+ ft.code_ = (cc & 0x0007) << 2 | 0;
GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
}
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