Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(117)

Side by Side Diff: src/mips/assembler-mips.cc

Issue 1365073002: Revert of Remove register index/code indirection (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 2 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/mips/assembler-mips.h ('k') | src/mips/assembler-mips-inl.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 46 matching lines...) Expand 10 before | Expand all | Expand 10 after
57 // generation even when generating snapshots. This won't work for cross 57 // generation even when generating snapshots. This won't work for cross
58 // compilation. 58 // compilation.
59 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0 59 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
60 answer |= 1u << FPU; 60 answer |= 1u << FPU;
61 #endif 61 #endif
62 62
63 return answer; 63 return answer;
64 } 64 }
65 65
66 66
67 const char* DoubleRegister::AllocationIndexToString(int index) {
68 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
69 const char* const names[] = {
70 "f0",
71 "f2",
72 "f4",
73 "f6",
74 "f8",
75 "f10",
76 "f12",
77 "f14",
78 "f16",
79 "f18",
80 "f20",
81 "f22",
82 "f24",
83 "f26"
84 };
85 return names[index];
86 }
87
88
67 void CpuFeatures::ProbeImpl(bool cross_compile) { 89 void CpuFeatures::ProbeImpl(bool cross_compile) {
68 supported_ |= CpuFeaturesImpliedByCompiler(); 90 supported_ |= CpuFeaturesImpliedByCompiler();
69 91
70 // Only use statically determined features for cross compile (snapshot). 92 // Only use statically determined features for cross compile (snapshot).
71 if (cross_compile) return; 93 if (cross_compile) return;
72 94
73 // If the compiler is allowed to use fpu then we can use fpu too in our 95 // If the compiler is allowed to use fpu then we can use fpu too in our
74 // code generation. 96 // code generation.
75 #ifndef __mips__ 97 #ifndef __mips__
76 // For the simulator build, use FPU. 98 // For the simulator build, use FPU.
(...skipping 144 matching lines...) Expand 10 before | Expand all | Expand 10 after
221 offset_ = unit * multiplier + offset_addend; 243 offset_ = unit * multiplier + offset_addend;
222 } 244 }
223 245
224 246
225 // ----------------------------------------------------------------------------- 247 // -----------------------------------------------------------------------------
226 // Specific instructions, constants, and masks. 248 // Specific instructions, constants, and masks.
227 249
228 static const int kNegOffset = 0x00008000; 250 static const int kNegOffset = 0x00008000;
229 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 251 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
230 // operations as post-increment of sp. 252 // operations as post-increment of sp.
231 const Instr kPopInstruction = ADDIU | (Register::kCode_sp << kRsShift) | 253 const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
232 (Register::kCode_sp << kRtShift) | 254 | (kRegister_sp_Code << kRtShift)
233 (kPointerSize & kImm16Mask); // NOLINT 255 | (kPointerSize & kImm16Mask); // NOLINT
234 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. 256 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
235 const Instr kPushInstruction = ADDIU | (Register::kCode_sp << kRsShift) | 257 const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
236 (Register::kCode_sp << kRtShift) | 258 | (kRegister_sp_Code << kRtShift)
237 (-kPointerSize & kImm16Mask); // NOLINT 259 | (-kPointerSize & kImm16Mask); // NOLINT
238 // sw(r, MemOperand(sp, 0)) 260 // sw(r, MemOperand(sp, 0))
239 const Instr kPushRegPattern = 261 const Instr kPushRegPattern = SW | (kRegister_sp_Code << kRsShift)
240 SW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT 262 | (0 & kImm16Mask); // NOLINT
241 // lw(r, MemOperand(sp, 0)) 263 // lw(r, MemOperand(sp, 0))
242 const Instr kPopRegPattern = 264 const Instr kPopRegPattern = LW | (kRegister_sp_Code << kRsShift)
243 LW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT 265 | (0 & kImm16Mask); // NOLINT
244 266
245 const Instr kLwRegFpOffsetPattern = 267 const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
246 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT 268 | (0 & kImm16Mask); // NOLINT
247 269
248 const Instr kSwRegFpOffsetPattern = 270 const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
249 SW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT 271 | (0 & kImm16Mask); // NOLINT
250 272
251 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) | 273 const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
252 (kNegOffset & kImm16Mask); // NOLINT 274 | (kNegOffset & kImm16Mask); // NOLINT
253 275
254 const Instr kSwRegFpNegOffsetPattern = SW | (Register::kCode_fp << kRsShift) | 276 const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
255 (kNegOffset & kImm16Mask); // NOLINT 277 | (kNegOffset & kImm16Mask); // NOLINT
256 // A mask for the Rt register for push, pop, lw, sw instructions. 278 // A mask for the Rt register for push, pop, lw, sw instructions.
257 const Instr kRtMask = kRtFieldMask; 279 const Instr kRtMask = kRtFieldMask;
258 const Instr kLwSwInstrTypeMask = 0xffe00000; 280 const Instr kLwSwInstrTypeMask = 0xffe00000;
259 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask; 281 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask;
260 const Instr kLwSwOffsetMask = kImm16Mask; 282 const Instr kLwSwOffsetMask = kImm16Mask;
261 283
262 284
263 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) 285 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
264 : AssemblerBase(isolate, buffer, buffer_size), 286 : AssemblerBase(isolate, buffer, buffer_size),
265 recorded_ast_id_(TypeFeedbackId::None()), 287 recorded_ast_id_(TypeFeedbackId::None()),
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
305 327
306 void Assembler::CodeTargetAlign() { 328 void Assembler::CodeTargetAlign() {
307 // No advantage to aligning branch/call targets to more than 329 // No advantage to aligning branch/call targets to more than
308 // single instruction, that I am aware of. 330 // single instruction, that I am aware of.
309 Align(4); 331 Align(4);
310 } 332 }
311 333
312 334
313 Register Assembler::GetRtReg(Instr instr) { 335 Register Assembler::GetRtReg(Instr instr) {
314 Register rt; 336 Register rt;
315 rt.reg_code = (instr & kRtFieldMask) >> kRtShift; 337 rt.code_ = (instr & kRtFieldMask) >> kRtShift;
316 return rt; 338 return rt;
317 } 339 }
318 340
319 341
320 Register Assembler::GetRsReg(Instr instr) { 342 Register Assembler::GetRsReg(Instr instr) {
321 Register rs; 343 Register rs;
322 rs.reg_code = (instr & kRsFieldMask) >> kRsShift; 344 rs.code_ = (instr & kRsFieldMask) >> kRsShift;
323 return rs; 345 return rs;
324 } 346 }
325 347
326 348
327 Register Assembler::GetRdReg(Instr instr) { 349 Register Assembler::GetRdReg(Instr instr) {
328 Register rd; 350 Register rd;
329 rd.reg_code = (instr & kRdFieldMask) >> kRdShift; 351 rd.code_ = (instr & kRdFieldMask) >> kRdShift;
330 return rd; 352 return rd;
331 } 353 }
332 354
333 355
334 uint32_t Assembler::GetRt(Instr instr) { 356 uint32_t Assembler::GetRt(Instr instr) {
335 return (instr & kRtFieldMask) >> kRtShift; 357 return (instr & kRtFieldMask) >> kRtShift;
336 } 358 }
337 359
338 360
339 uint32_t Assembler::GetRtField(Instr instr) { 361 uint32_t Assembler::GetRtField(Instr instr) {
(...skipping 1573 matching lines...) Expand 10 before | Expand all | Expand 10 after
1913 } 1935 }
1914 1936
1915 1937
1916 void Assembler::movn(Register rd, Register rs, Register rt) { 1938 void Assembler::movn(Register rd, Register rs, Register rt) {
1917 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); 1939 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
1918 } 1940 }
1919 1941
1920 1942
1921 void Assembler::movt(Register rd, Register rs, uint16_t cc) { 1943 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
1922 Register rt; 1944 Register rt;
1923 rt.reg_code = (cc & 0x0007) << 2 | 1; 1945 rt.code_ = (cc & 0x0007) << 2 | 1;
1924 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); 1946 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1925 } 1947 }
1926 1948
1927 1949
1928 void Assembler::movf(Register rd, Register rs, uint16_t cc) { 1950 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
1929 Register rt; 1951 Register rt;
1930 rt.reg_code = (cc & 0x0007) << 2 | 0; 1952 rt.code_ = (cc & 0x0007) << 2 | 0;
1931 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); 1953 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1932 } 1954 }
1933 1955
1934 1956
1935 void Assembler::seleqz(Register rd, Register rs, Register rt) { 1957 void Assembler::seleqz(Register rd, Register rs, Register rt) {
1936 DCHECK(IsMipsArchVariant(kMips32r6)); 1958 DCHECK(IsMipsArchVariant(kMips32r6));
1937 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); 1959 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
1938 } 1960 }
1939 1961
1940 1962
(...skipping 263 matching lines...) Expand 10 before | Expand all | Expand 10 after
2204 2226
2205 void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) { 2227 void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) {
2206 DCHECK(IsMipsArchVariant(kMips32r2)); 2228 DCHECK(IsMipsArchVariant(kMips32r2));
2207 GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C); 2229 GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C);
2208 } 2230 }
2209 2231
2210 2232
2211 void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) { 2233 void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2212 DCHECK(IsMipsArchVariant(kMips32r2)); 2234 DCHECK(IsMipsArchVariant(kMips32r2));
2213 FPURegister ft; 2235 FPURegister ft;
2214 ft.reg_code = (cc & 0x0007) << 2 | 1; 2236 ft.code_ = (cc & 0x0007) << 2 | 1;
2215 GenInstrRegister(COP1, S, ft, fs, fd, MOVF); 2237 GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
2216 } 2238 }
2217 2239
2218 2240
2219 void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) { 2241 void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2220 DCHECK(IsMipsArchVariant(kMips32r2)); 2242 DCHECK(IsMipsArchVariant(kMips32r2));
2221 FPURegister ft; 2243 FPURegister ft;
2222 ft.reg_code = (cc & 0x0007) << 2 | 1; 2244 ft.code_ = (cc & 0x0007) << 2 | 1;
2223 GenInstrRegister(COP1, D, ft, fs, fd, MOVF); 2245 GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
2224 } 2246 }
2225 2247
2226 2248
2227 void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) { 2249 void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2228 DCHECK(IsMipsArchVariant(kMips32r2)); 2250 DCHECK(IsMipsArchVariant(kMips32r2));
2229 FPURegister ft; 2251 FPURegister ft;
2230 ft.reg_code = (cc & 0x0007) << 2 | 0; 2252 ft.code_ = (cc & 0x0007) << 2 | 0;
2231 GenInstrRegister(COP1, S, ft, fs, fd, MOVF); 2253 GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
2232 } 2254 }
2233 2255
2234 2256
2235 void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) { 2257 void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2236 DCHECK(IsMipsArchVariant(kMips32r2)); 2258 DCHECK(IsMipsArchVariant(kMips32r2));
2237 FPURegister ft; 2259 FPURegister ft;
2238 ft.reg_code = (cc & 0x0007) << 2 | 0; 2260 ft.code_ = (cc & 0x0007) << 2 | 0;
2239 GenInstrRegister(COP1, D, ft, fs, fd, MOVF); 2261 GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
2240 } 2262 }
2241 2263
2242 2264
2243 // Arithmetic. 2265 // Arithmetic.
2244 2266
2245 void Assembler::add_s(FPURegister fd, FPURegister fs, FPURegister ft) { 2267 void Assembler::add_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2246 GenInstrRegister(COP1, S, ft, fs, fd, ADD_S); 2268 GenInstrRegister(COP1, S, ft, fs, fd, ADD_S);
2247 } 2269 }
2248 2270
(...skipping 825 matching lines...) Expand 10 before | Expand all | Expand 10 after
3074 if (patched) { 3096 if (patched) {
3075 CpuFeatures::FlushICache(pc + 2, sizeof(Address)); 3097 CpuFeatures::FlushICache(pc + 2, sizeof(Address));
3076 } 3098 }
3077 } 3099 }
3078 3100
3079 3101
3080 } // namespace internal 3102 } // namespace internal
3081 } // namespace v8 3103 } // namespace v8
3082 3104
3083 #endif // V8_TARGET_ARCH_MIPS 3105 #endif // V8_TARGET_ARCH_MIPS
OLDNEW
« no previous file with comments | « src/mips/assembler-mips.h ('k') | src/mips/assembler-mips-inl.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698