Index: src/IceTargetLoweringARM32.def |
diff --git a/src/IceTargetLoweringARM32.def b/src/IceTargetLoweringARM32.def |
index a004cb66fd4ebfe2555837b77bed5e049b8c6112..c4c2af1673f512f0595892a0cbb6c0444261a8f0 100644 |
--- a/src/IceTargetLoweringARM32.def |
+++ b/src/IceTargetLoweringARM32.def |
@@ -15,6 +15,34 @@ |
#ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF |
#define SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF |
+// Patterns for lowering fcmp. These are expected to be used in the following |
+// manner: |
+// |
+// mov reg, #0 |
+// movCC0 reg, #1 /* only if CC0 != kNone */ |
+// movCC1 reg, #1 /* only if CC1 != kNone */ |
+// |
+// TODO(jpp): vector lowerings. |
+#define FCMPARM32_TABLE \ |
Jim Stichnoth
2015/09/18 19:28:55
Can you align all the continuation backslashes at
John
2015/09/18 22:55:53
Done.
|
+ /* val, CC0, CC1 */ \ |
+ X(False, kNone, kNone) \ |
+ X(Oeq, EQ, kNone) \ |
+ X(Ogt, GT, kNone) \ |
+ X(Oge, GE, kNone) \ |
+ X(Olt, MI, kNone) \ |
+ X(Ole, LS, kNone) \ |
+ X(One, MI, GT) \ |
+ X(Ord, VC, kNone) \ |
+ X(Ueq, EQ, VS) \ |
+ X(Ugt, HI, kNone) \ |
+ X(Uge, PL, kNone) \ |
+ X(Ult, LT, kNone) \ |
+ X(Ule, LE, kNone) \ |
+ X(Une, NE, kNone) \ |
+ X(Uno, VS, kNone) \ |
+ X(True, AL, kNone) \ |
+//#define X(val, CC0, CC1) |
+ |
// Patterns for lowering icmp. |
#define ICMPARM32_TABLE \ |
/* val, is_signed, swapped64, C_32, C1_64, C2_64 */ \ |