Subzero. Fixes ARM32 VFP calling convention.

src/IceTargetLoweringARM32.h

Index: src/IceTargetLoweringARM32.h
diff --git a/src/IceTargetLoweringARM32.h b/src/IceTargetLoweringARM32.h
index 57e0b5ab6fa1811f34639f4a3df73e37af500f02..7e54372b3c55c0662b32e6555459beb43d93fce1 100644
--- a/src/IceTargetLoweringARM32.h
+++ b/src/IceTargetLoweringARM32.h
@@ -21,6 +21,8 @@
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
+#include "llvm/ADT/SmallBitVector.h"
+
 namespace Ice {
 
 // Class encapsulating ARM cpu features / instruction set.
@@ -476,7 +478,19 @@ protected:
     CallingConv &operator=(const CallingConv &) = delete;
 
   public:
-    CallingConv() {}
+    CallingConv()
+        : VFPRegsFree(ARM32_MAX_FP_REG_UNITS, true),
+          ValidF64Regs(ARM32_MAX_FP_REG_UNITS),
+          ValidV128Regs(ARM32_MAX_FP_REG_UNITS) {
+      for (uint32_t i = 0; i < ARM32_MAX_FP_REG_UNITS; ++i) {

[Jim Stichnoth, 2015/09/16 21:31:54]

Whoa!  This is almost FizzBuzz!
:)

+        if ((i % 2) == 0) {
+          ValidF64Regs[i] = true;
+        }
+        if ((i % 4) == 0) {
+          ValidV128Regs[i] = true;
+        }
+      }
+    }
     ~CallingConv() = default;
 
     bool I64InRegs(std::pair<int32_t, int32_t> *Regs);
@@ -484,12 +498,14 @@ protected:
     bool FPInReg(Type Ty, int32_t *Reg);
 
     static constexpr uint32_t ARM32_MAX_GPR_ARG = 4;
-    // Units of S registers still available to S/D/Q arguments.
+    // TODO(jpp): comment.
     static constexpr uint32_t ARM32_MAX_FP_REG_UNITS = 16;
 
   private:
     uint32_t NumGPRRegsUsed = 0;
-    uint32_t NumFPRegUnits = 0;
+    llvm::SmallBitVector VFPRegsFree;
+    llvm::SmallBitVector ValidF64Regs;
+    llvm::SmallBitVector ValidV128Regs;
   };
 
 private: