Subzero. Fixes ARM32 VFP calling convention.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file declares the TargetLoweringARM32 class, which implements the
 /// TargetLowering interface for the ARM 32-bit architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 
 #include "IceDefs.h"
 #include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
+#include "llvm/ADT/SmallBitVector.h"
+
 namespace Ice {
 
 // Class encapsulating ARM cpu features / instruction set.
 class TargetARM32Features {
   TargetARM32Features() = delete;
   TargetARM32Features(const TargetARM32Features &) = delete;
   TargetARM32Features &operator=(const TargetARM32Features &) = delete;
 
 public:
   explicit TargetARM32Features(const ClFlags &Flags);
@@ skipping 421 matching lines @@
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
   llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
 
   /// Helper class that understands the Calling Convention and register
   /// assignments. The first few integer type parameters can use r0-r3,

[Jim Stichnoth, 2015/09/16 21:31:54]

Is there a public reference that you can cite here for the interested reader?

[John, 2015/09/16 23:12:47]

Done.

   /// regardless of their position relative to the floating-point/vector
   /// arguments in the argument list. Floating-point and vector arguments
   /// can use q0-q3 (aka d0-d7, s0-s15). Technically, arguments that can
   /// start with registers but extend beyond the available registers can be
   /// split between the registers and the stack. However, this is typically
   /// for passing GPR structs by value, and PNaCl transforms expand this out.
   ///
   /// Also, at the point before the call, the stack must be aligned.
   class CallingConv {
     CallingConv(const CallingConv &) = delete;
     CallingConv &operator=(const CallingConv &) = delete;
 
   public:
-    CallingConv() {}
+    CallingConv()
+        : VFPRegsFree(ARM32_MAX_FP_REG_UNITS, true),
+          ValidF64Regs(ARM32_MAX_FP_REG_UNITS),
+          ValidV128Regs(ARM32_MAX_FP_REG_UNITS) {
+      for (uint32_t i = 0; i < ARM32_MAX_FP_REG_UNITS; ++i) {

[Jim Stichnoth, 2015/09/16 21:31:54]

Whoa!  This is almost FizzBuzz!
:)

+        if ((i % 2) == 0) {
+          ValidF64Regs[i] = true;
+        }
+        if ((i % 4) == 0) {
+          ValidV128Regs[i] = true;
+        }
+      }
+    }
     ~CallingConv() = default;
 
     bool I64InRegs(std::pair<int32_t, int32_t> *Regs);
     bool I32InReg(int32_t *Reg);
     bool FPInReg(Type Ty, int32_t *Reg);
 
     static constexpr uint32_t ARM32_MAX_GPR_ARG = 4;
-    // Units of S registers still available to S/D/Q arguments.
+    // TODO(jpp): comment.
     static constexpr uint32_t ARM32_MAX_FP_REG_UNITS = 16;
 
   private:
     uint32_t NumGPRRegsUsed = 0;
-    uint32_t NumFPRegUnits = 0;
+    llvm::SmallBitVector VFPRegsFree;
+    llvm::SmallBitVector ValidF64Regs;
+    llvm::SmallBitVector ValidV128Regs;
   };
 
 private:
   ~TargetARM32() override = default;
 };
 
 class TargetDataARM32 final : public TargetDataLowering {
   TargetDataARM32() = delete;
   TargetDataARM32(const TargetDataARM32 &) = delete;
   TargetDataARM32 &operator=(const TargetDataARM32 &) = delete;
@@ skipping 33 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H