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src/IceTargetLoweringX8664Traits.h

Index: src/IceTargetLoweringX8664Traits.h
diff --git a/src/IceTargetLoweringX8664Traits.h b/src/IceTargetLoweringX8664Traits.h
index 454b6cb82d214acf1a9c719c9b0994bf911a8e1b..0ed40a862001da2e8bccc3239ea8a8f8adf5060f 100644
--- a/src/IceTargetLoweringX8664Traits.h
+++ b/src/IceTargetLoweringX8664Traits.h
@@ -404,10 +404,10 @@ template <> struct MachineTraits<TargetX8664> {
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) {
     // TODO(stichnot): Declaring Permutation this way loses type/size
-    // information.  Fix this in conjunction with the caller-side TODO.
+    // information. Fix this in conjunction with the caller-side TODO.
     assert(Permutation.size() >= RegisterSet::Reg_NUM);
     // Expected upper bound on the number of registers in a single equivalence
-    // class.  For x86-64, this would comprise the 16 XMM registers.  This is
+    // class.  For x86-64, this would comprise the 16 XMM registers. This is
     // for performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>;
@@ -493,8 +493,8 @@ template <> struct MachineTraits<TargetX8664> {
   static constexpr uint32_t MEMSET_UNROLL_LIMIT = 16;
   /// @}
 
-  /// Value is in bytes. Return Value adjusted to the next highest multiple
-  /// of the stack alignment.
+  /// Value is in bytes. Return Value adjusted to the next highest multiple of
+  /// the stack alignment.
   static uint32_t applyStackAlignment(uint32_t Value) {
     return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
   }
@@ -516,17 +516,17 @@ template <> struct MachineTraits<TargetX8664> {
   /// instruction. There is one table entry for each of the 16 conditions.
   ///
   /// The first four columns describe the case when the operands are floating
-  /// point scalar values.  A comment in lowerFcmp() describes the lowering
-  /// template.  In the most general case, there is a compare followed by two
+  /// point scalar values. A comment in lowerFcmp() describes the lowering
+  /// template. In the most general case, there is a compare followed by two
   /// conditional branches, because some fcmp conditions don't map to a single
-  /// x86 conditional branch.  However, in many cases it is possible to swap the
-  /// operands in the comparison and have a single conditional branch.  Since
+  /// x86 conditional branch. However, in many cases it is possible to swap the
+  /// operands in the comparison and have a single conditional branch. Since
   /// it's quite tedious to validate the table by hand, good execution tests are
   /// helpful.
   ///
   /// The last two columns describe the case when the operands are vectors of
-  /// floating point values.  For most fcmp conditions, there is a clear mapping
-  /// to a single x86 cmpps instruction variant.  Some fcmp conditions require
+  /// floating point values. For most fcmp conditions, there is a clear mapping
+  /// to a single x86 cmpps instruction variant. Some fcmp conditions require
   /// special code to handle and these are marked in the table with a
   /// Cmpps_Invalid predicate.
   /// {@
@@ -541,7 +541,7 @@ template <> struct MachineTraits<TargetX8664> {
   /// @}
 
   /// The following table summarizes the logic for lowering the icmp instruction
-  /// for i32 and narrower types.  Each icmp condition has a clear mapping to an
+  /// for i32 and narrower types. Each icmp condition has a clear mapping to an
   /// x86 conditional branch instruction.
   /// {@
   static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
@@ -549,8 +549,8 @@ template <> struct MachineTraits<TargetX8664> {
   /// @}
 
   /// The following table summarizes the logic for lowering the icmp instruction
-  /// for the i64 type.  For Eq and Ne, two separate 32-bit comparisons and
-  /// conditional branches are needed.  For the other conditions, three separate
+  /// for the i64 type. For Eq and Ne, two separate 32-bit comparisons and
+  /// conditional branches are needed. For the other conditions, three separate
   /// conditional branches are needed.
   /// {@
   static const struct TableIcmp64Type {
@@ -583,8 +583,8 @@ template <> struct MachineTraits<TargetX8664> {
   using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8664>;
   using Assembler = X8664::AssemblerX8664;
 
-  /// X86Operand extends the Operand hierarchy.  Its subclasses are
-  /// X86OperandMem and VariableSplit.
+  /// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem
+  /// and VariableSplit.
   class X86Operand : public ::Ice::Operand {
     X86Operand() = delete;
     X86Operand(const X86Operand &) = delete;
@@ -655,8 +655,8 @@ template <> struct MachineTraits<TargetX8664> {
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32
-  /// locations (Low and High).  This is needed for some cases of the Bitcast
-  /// instruction.  Since it's not possible for integer registers to access the
+  /// locations (Low and High). This is needed for some cases of the Bitcast
+  /// instruction. Since it's not possible for integer registers to access the
   /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
   /// the stack and then accesses through the VariableSplit.
   // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit
@@ -696,11 +696,11 @@ template <> struct MachineTraits<TargetX8664> {
     Portion Part;
   };
 
-  /// SpillVariable decorates a Variable by linking it to another Variable.
-  /// When stack frame offsets are computed, the SpillVariable is given a
-  /// distinct stack slot only if its linked Variable has a register.  If the
-  /// linked Variable has a stack slot, then the Variable and SpillVariable
-  /// share that slot.
+  /// SpillVariable decorates a Variable by linking it to another Variable. When
+  /// stack frame offsets are computed, the SpillVariable is given a distinct
+  /// stack slot only if its linked Variable has a register. If the linked
+  /// Variable has a stack slot, then the Variable and SpillVariable share that
+  /// slot.
   class SpillVariable : public Variable {
     SpillVariable() = delete;
     SpillVariable(const SpillVariable &) = delete;