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src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 386 matching lines @@
 
     return Registers;
   }
 
   static void
   makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func,
                                 llvm::SmallVectorImpl<int32_t> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) {
     // TODO(stichnot): Declaring Permutation this way loses type/size
-    // information.  Fix this in conjunction with the caller-side TODO.
+    // information. Fix this in conjunction with the caller-side TODO.
     assert(Permutation.size() >= RegisterSet::Reg_NUM);
     // Expected upper bound on the number of registers in a single equivalence
-    // class.  For x86-64, this would comprise the 16 XMM registers.  This is
+    // class.  For x86-64, this would comprise the 16 XMM registers. This is
     // for performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>;
     using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
     EquivalenceClassMap EquivalenceClasses;
     SizeT NumShuffled = 0, NumPreserved = 0;
 
 // Build up the equivalence classes of registers by looking at the register
 // properties as well as whether the registers should be explicitly excluded
 // from shuffling.
@@ skipping 65 matching lines @@
   /// The number of different NOP instructions
   static const uint32_t X86_NUM_NOP_VARIANTS = 5;
 
   /// \name Limits for unrolling memory intrinsics.
   /// @{
   static constexpr uint32_t MEMCPY_UNROLL_LIMIT = 8;
   static constexpr uint32_t MEMMOVE_UNROLL_LIMIT = 8;
   static constexpr uint32_t MEMSET_UNROLL_LIMIT = 16;
   /// @}
 
-  /// Value is in bytes. Return Value adjusted to the next highest multiple
-  /// of the stack alignment.
+  /// Value is in bytes. Return Value adjusted to the next highest multiple of
+  /// the stack alignment.
   static uint32_t applyStackAlignment(uint32_t Value) {
     return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
   }
 
   /// Return the type which the elements of the vector have in the X86
   /// representation of the vector.
   static Type getInVectorElementType(Type Ty) {
     assert(isVectorType(Ty));
     size_t Index = static_cast<size_t>(Ty);
     (void)Index;
     assert(Index < TableTypeX8664AttributesSize);
     return TableTypeX8664Attributes[Ty].InVectorElementType;
   }
 
   // Note: The following data structures are defined in
   // IceTargetLoweringX8664.cpp.
 
   /// The following table summarizes the logic for lowering the fcmp
   /// instruction. There is one table entry for each of the 16 conditions.
   ///
   /// The first four columns describe the case when the operands are floating
-  /// point scalar values.  A comment in lowerFcmp() describes the lowering
-  /// template.  In the most general case, there is a compare followed by two
+  /// point scalar values. A comment in lowerFcmp() describes the lowering
+  /// template. In the most general case, there is a compare followed by two
   /// conditional branches, because some fcmp conditions don't map to a single
-  /// x86 conditional branch.  However, in many cases it is possible to swap the
-  /// operands in the comparison and have a single conditional branch.  Since
+  /// x86 conditional branch. However, in many cases it is possible to swap the
+  /// operands in the comparison and have a single conditional branch. Since
   /// it's quite tedious to validate the table by hand, good execution tests are
   /// helpful.
   ///
   /// The last two columns describe the case when the operands are vectors of
-  /// floating point values.  For most fcmp conditions, there is a clear mapping
-  /// to a single x86 cmpps instruction variant.  Some fcmp conditions require
+  /// floating point values. For most fcmp conditions, there is a clear mapping
+  /// to a single x86 cmpps instruction variant. Some fcmp conditions require
   /// special code to handle and these are marked in the table with a
   /// Cmpps_Invalid predicate.
   /// {@
   static const struct TableFcmpType {
     uint32_t Default;
     bool SwapScalarOperands;
     Cond::BrCond C1, C2;
     bool SwapVectorOperands;
     Cond::CmppsCond Predicate;
   } TableFcmp[];
   static const size_t TableFcmpSize;
   /// @}
 
   /// The following table summarizes the logic for lowering the icmp instruction
-  /// for i32 and narrower types.  Each icmp condition has a clear mapping to an
+  /// for i32 and narrower types. Each icmp condition has a clear mapping to an
   /// x86 conditional branch instruction.
   /// {@
   static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
   static const size_t TableIcmp32Size;
   /// @}
 
   /// The following table summarizes the logic for lowering the icmp instruction
-  /// for the i64 type.  For Eq and Ne, two separate 32-bit comparisons and
-  /// conditional branches are needed.  For the other conditions, three separate
+  /// for the i64 type. For Eq and Ne, two separate 32-bit comparisons and
+  /// conditional branches are needed. For the other conditions, three separate
   /// conditional branches are needed.
   /// {@
   static const struct TableIcmp64Type {
     Cond::BrCond C1, C2, C3;
   } TableIcmp64[];
   static const size_t TableIcmp64Size;
   /// @}
 
   static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
     size_t Index = static_cast<size_t>(Cond);
@@ skipping 12 matching lines @@
   //    \ \ \ \ \-.  \ \___  \/_/\ \/
   //     \ \_\ \_\\"\_\/\_____\ \ \_\
   //      \/_/\/_/ \/_/\/_____/  \/_/
   //
   //----------------------------------------------------------------------------
   using Insts = ::Ice::X86Internal::Insts<TargetX8664>;
 
   using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8664>;
   using Assembler = X8664::AssemblerX8664;
 
-  /// X86Operand extends the Operand hierarchy.  Its subclasses are
-  /// X86OperandMem and VariableSplit.
+  /// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem
+  /// and VariableSplit.
   class X86Operand : public ::Ice::Operand {
     X86Operand() = delete;
     X86Operand(const X86Operand &) = delete;
     X86Operand &operator=(const X86Operand &) = delete;
 
   public:
     enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
     using ::Ice::Operand::dump;
 
     void dump(const Cfg *, Ostream &Str) const override;
@@ skipping 50 matching lines @@
     Constant *Offset;
     Variable *Index;
     uint16_t Shift;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()
     bool Randomized = false;
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32
-  /// locations (Low and High).  This is needed for some cases of the Bitcast
-  /// instruction.  Since it's not possible for integer registers to access the
+  /// locations (Low and High). This is needed for some cases of the Bitcast
+  /// instruction. Since it's not possible for integer registers to access the
   /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
   /// the stack and then accesses through the VariableSplit.
   // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit
   // targets can natively handle these.
   class VariableSplit : public X86Operand {
     VariableSplit() = delete;
     VariableSplit(const VariableSplit &) = delete;
     VariableSplit &operator=(const VariableSplit &) = delete;
 
   public:
@@ skipping 19 matching lines @@
       assert(Var->getType() == IceType_f64);
       Vars = Func->allocateArrayOf<Variable *>(1);
       Vars[0] = Var;
       NumVars = 1;
     }
 
     Variable *Var;
     Portion Part;
   };
 
-  /// SpillVariable decorates a Variable by linking it to another Variable.
-  /// When stack frame offsets are computed, the SpillVariable is given a
-  /// distinct stack slot only if its linked Variable has a register.  If the
-  /// linked Variable has a stack slot, then the Variable and SpillVariable
-  /// share that slot.
+  /// SpillVariable decorates a Variable by linking it to another Variable. When
+  /// stack frame offsets are computed, the SpillVariable is given a distinct
+  /// stack slot only if its linked Variable has a register. If the linked
+  /// Variable has a stack slot, then the Variable and SpillVariable share that
+  /// slot.
   class SpillVariable : public Variable {
     SpillVariable() = delete;
     SpillVariable(const SpillVariable &) = delete;
     SpillVariable &operator=(const SpillVariable &) = delete;
 
   public:
     static SpillVariable *create(Cfg *Func, Type Ty, SizeT Index) {
       return new (Func->allocate<SpillVariable>()) SpillVariable(Ty, Index);
     }
     const static OperandKind SpillVariableKind =
@@ skipping 34 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8664 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H