| Index: src/a64/macro-assembler-a64.cc
|
| diff --git a/src/a64/macro-assembler-a64.cc b/src/a64/macro-assembler-a64.cc
|
| index b509d74bdf521fc5eff33f83825bda35335db015..38fcc419da778b3517525e05050e673b444d92b8 100644
|
| --- a/src/a64/macro-assembler-a64.cc
|
| +++ b/src/a64/macro-assembler-a64.cc
|
| @@ -519,6 +519,46 @@ void MacroAssembler::LoadStoreMacro(const CPURegister& rt,
|
| }
|
|
|
|
|
| +void MacroAssembler::Load(const Register& rt,
|
| + const MemOperand& addr,
|
| + Representation r) {
|
| + ASSERT(!r.IsDouble());
|
| +
|
| + if (r.IsInteger8()) {
|
| + Ldrsb(rt, addr);
|
| + } else if (r.IsUInteger8()) {
|
| + Ldrb(rt, addr);
|
| + } else if (r.IsInteger16()) {
|
| + Ldrsh(rt, addr);
|
| + } else if (r.IsUInteger16()) {
|
| + Ldrh(rt, addr);
|
| + } else if (r.IsInteger32()) {
|
| + Ldr(rt.W(), addr);
|
| + } else {
|
| + ASSERT(rt.Is64Bits());
|
| + Ldr(rt, addr);
|
| + }
|
| +}
|
| +
|
| +
|
| +void MacroAssembler::Store(const Register& rt,
|
| + const MemOperand& addr,
|
| + Representation r) {
|
| + ASSERT(!r.IsDouble());
|
| +
|
| + if (r.IsInteger8() || r.IsUInteger8()) {
|
| + Strb(rt, addr);
|
| + } else if (r.IsInteger16() || r.IsUInteger16()) {
|
| + Strh(rt, addr);
|
| + } else if (r.IsInteger32()) {
|
| + Str(rt.W(), addr);
|
| + } else {
|
| + ASSERT(rt.Is64Bits());
|
| + Str(rt, addr);
|
| + }
|
| +}
|
| +
|
| +
|
| // Pseudo-instructions.
|
|
|
|
|
|
|