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| 1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 512 // Pre-index beyond unscaled addressing range. | 512 // Pre-index beyond unscaled addressing range. |
| 513 add(addr.base(), addr.base(), offset); | 513 add(addr.base(), addr.base(), offset); |
| 514 LoadStore(rt, MemOperand(addr.base()), op); | 514 LoadStore(rt, MemOperand(addr.base()), op); |
| 515 } else { | 515 } else { |
| 516 // Encodable in one load/store instruction. | 516 // Encodable in one load/store instruction. |
| 517 LoadStore(rt, addr, op); | 517 LoadStore(rt, addr, op); |
| 518 } | 518 } |
| 519 } | 519 } |
| 520 | 520 |
| 521 | 521 |
| 522 void MacroAssembler::Load(const Register& rt, |
| 523 const MemOperand& addr, |
| 524 Representation r) { |
| 525 ASSERT(!r.IsDouble()); |
| 526 |
| 527 if (r.IsInteger8()) { |
| 528 Ldrsb(rt, addr); |
| 529 } else if (r.IsUInteger8()) { |
| 530 Ldrb(rt, addr); |
| 531 } else if (r.IsInteger16()) { |
| 532 Ldrsh(rt, addr); |
| 533 } else if (r.IsUInteger16()) { |
| 534 Ldrh(rt, addr); |
| 535 } else if (r.IsInteger32()) { |
| 536 Ldr(rt.W(), addr); |
| 537 } else { |
| 538 ASSERT(rt.Is64Bits()); |
| 539 Ldr(rt, addr); |
| 540 } |
| 541 } |
| 542 |
| 543 |
| 544 void MacroAssembler::Store(const Register& rt, |
| 545 const MemOperand& addr, |
| 546 Representation r) { |
| 547 ASSERT(!r.IsDouble()); |
| 548 |
| 549 if (r.IsInteger8() || r.IsUInteger8()) { |
| 550 Strb(rt, addr); |
| 551 } else if (r.IsInteger16() || r.IsUInteger16()) { |
| 552 Strh(rt, addr); |
| 553 } else if (r.IsInteger32()) { |
| 554 Str(rt.W(), addr); |
| 555 } else { |
| 556 ASSERT(rt.Is64Bits()); |
| 557 Str(rt, addr); |
| 558 } |
| 559 } |
| 560 |
| 561 |
| 522 // Pseudo-instructions. | 562 // Pseudo-instructions. |
| 523 | 563 |
| 524 | 564 |
| 525 void MacroAssembler::Abs(const Register& rd, const Register& rm, | 565 void MacroAssembler::Abs(const Register& rd, const Register& rm, |
| 526 Label* is_not_representable, | 566 Label* is_not_representable, |
| 527 Label* is_representable) { | 567 Label* is_representable) { |
| 528 ASSERT(allow_macro_instructions_); | 568 ASSERT(allow_macro_instructions_); |
| 529 ASSERT(AreSameSizeAndType(rd, rm)); | 569 ASSERT(AreSameSizeAndType(rd, rm)); |
| 530 | 570 |
| 531 Cmp(rm, 1); | 571 Cmp(rm, 1); |
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| 4718 } | 4758 } |
| 4719 } | 4759 } |
| 4720 | 4760 |
| 4721 | 4761 |
| 4722 #undef __ | 4762 #undef __ |
| 4723 | 4763 |
| 4724 | 4764 |
| 4725 } } // namespace v8::internal | 4765 } } // namespace v8::internal |
| 4726 | 4766 |
| 4727 #endif // V8_TARGET_ARCH_A64 | 4767 #endif // V8_TARGET_ARCH_A64 |
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