Adds MIPS SPECIAL instructions to simulator, assembler, debugger.

runtime/vm/disassembler_mips.cc

Index: runtime/vm/disassembler_mips.cc
===================================================================
--- runtime/vm/disassembler_mips.cc	(revision 20092)
+++ runtime/vm/disassembler_mips.cc	(working copy)
@@ -229,6 +229,14 @@
       Format(instr, "divu 'rs, 'rt");
       break;
     }
+    case JALR: {
+      Format(instr, "jalr'hint 'rd, 'rs");
+      break;
+    }
+    case JR: {
+      Format(instr, "jr'hint 'rs");
+      break;
+    }
     case MFHI: {
       Format(instr, "mfhi 'rd");
       break;
@@ -237,6 +245,36 @@
       Format(instr, "mflo 'rd");
       break;
     }
+    case MOVN: {
+      Format(instr, "movn 'rd, 'rs, 'rt");
+      break;
+    }
+    case MOVZ: {
+      Format(instr, "movz 'rd, 'rs, 'rt");
+      break;
+    }
+    case MULT: {
+      Format(instr, "mult 'rs, 'rt");
+      break;
+    }
+    case MULTU: {
+      Format(instr, "multu 'rs, 'rt");
+      break;
+    }
+    case NOR: {
+      Format(instr, "nor 'rd, 'rs, 'rt");
+      break;
+    }
+    case OR: {
+      if (instr->RsField() == R0) {
+        Format(instr, "mov 'rd, 'rt");

[Ivan Posva, 2013/03/20 01:54:51]

Is the expectation that if it is "or RD, R0, R0" that we print "mov RD, R0", or
should we print "mov RD, 0"? That would be closer to "addi RT, RS, 1".

[zra, 2013/03/20 15:53:50]

Done.

+      } else if (instr->RtField() == R0) {
+        Format(instr, "mov 'rd, 'rs");
+      } else {
+        Format(instr, "or 'rd, 'rs, 'rt");
+      }
+      break;
+    }
     case SLL: {
       if ((instr->RdField() == R0) &&
           (instr->RtField() == R0) &&
@@ -247,10 +285,54 @@
       }
       break;
     }
-    case JR: {
-      Format(instr, "jr'hint 'rs");
+    case SLLV: {
+      Format(instr, "sllv 'rd, 'rt, 'rs");
       break;
     }
+    case SLT: {
+      Format(instr, "slt 'rd, 'rs, 'rt");
+      break;
+    }
+    case SLTU: {
+      Format(instr, "sltu 'rd, 'rs, 'rt");
+      break;
+    }
+    case SRA: {
+      Format(instr, "sra 'rd, 'rt, 'sa");

[Ivan Posva, 2013/03/20 01:54:51]

Here and others: The SRA instruction expects the RS field to be 0. We should
either assert or have some other safeguard against bad decodings.

[zra, 2013/03/20 15:53:50]

In the assembler, sra() passes 0 for rs to EmitRType, and the simulator asserts
that the RS field is 0. We can't put that assert into the disassembler because
dying while decoding an instruction would cause the SimulatorDebugger to die in
the middle of a debugging session (e.g. if you disasm  something that isn't
really instructions).

[Ivan Posva, 2013/03/21 00:08:06]

You could do Unkown(instr) like you do in SRL.

+      break;
+    }
+    case SRAV: {
+      Format(instr, "srav 'rd, 'rt, 'rs");
+      break;
+    }
+    case SRL: {
+      if (instr->RsField() == 0) {
+        Format(instr, "srl 'rd, 'rt, 'sa");
+      } else {
+        Unknown(instr);
+      }
+      break;
+    }
+    case SRLV: {
+      if (instr->SaField() == 0) {
+        Format(instr, "srlv 'rd, 'rt, 'rs");
+      } else {
+        Unknown(instr);
+      }
+      break;
+    }
+    case SUB: {
+      Format(instr, "sub 'rd, 'rs, 'rt");
+      break;
+    }
+    case SUBU: {
+      Format(instr, "subu 'rd, 'rs, 'rt");
+      break;
+    }
+    case XOR: {
+      Format(instr, "xor 'rd, 'rs, 'rt");
+      break;
+    }
     default: {
       Unknown(instr);
       break;