Chromium Code Reviews| Index: src/IceAssemblerX86BaseImpl.h |
| diff --git a/src/IceAssemblerX86BaseImpl.h b/src/IceAssemblerX86BaseImpl.h |
| index f78575682cc52f16d87488d694244881dc9b7f68..602ae15053d3c30c3aed3a8f5b4f174fd3c13fb5 100644 |
| --- a/src/IceAssemblerX86BaseImpl.h |
| +++ b/src/IceAssemblerX86BaseImpl.h |
| @@ -3099,6 +3099,30 @@ void AssemblerX86Base<Machine>::xadd(Type Ty, |
| template <class Machine> |
| void AssemblerX86Base<Machine>::xchg(Type Ty, |
| + typename Traits::GPRRegister reg0, |
| + typename Traits::GPRRegister reg1) { |
| + AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
| + if (Ty == IceType_i16) |
| + emitOperandSizeOverride(); |
| + // Use short form if either register is EAX. |
| + if (reg0 == Traits::Encoded_Reg_Accumulator) { |
| + emitRexB(Ty, reg1); |
| + emitUint8(0x90 + reg1); |
|
John
2015/08/12 17:44:57
emitUint8(0x90 + gprEncoding(reg1));
ascull
2015/08/17 22:18:52
Done.
|
| + } else if (reg1 == Traits::Encoded_Reg_Accumulator) { |
| + emitRexB(Ty, reg0); |
| + emitUint8(0x90 + reg0); |
|
John
2015/08/12 17:44:57
emitUint8(0x90 + gprEncoding(reg0));
ascull
2015/08/17 22:18:52
Done. Incl also only does `+ reg` is that a proble
|
| + } else { |
| + emitRexRB(Ty, reg0, reg1); |
| + if (isByteSizedArithType(Ty)) |
| + emitUint8(0x86); |
| + else |
| + emitUint8(0x87); |
| + emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); |
| + } |
| +} |
| + |
| +template <class Machine> |
| +void AssemblerX86Base<Machine>::xchg(Type Ty, |
| const typename Traits::Address &addr, |
| typename Traits::GPRRegister reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&Buffer); |