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Side by Side Diff: src/IceAssemblerX86BaseImpl.h

Issue 1278173009: Inline memove for small constant sizes and refactor memcpy and memset. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 4 months ago
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1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=//
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
3 // for details. All rights reserved. Use of this source code is governed by a 3 // for details. All rights reserved. Use of this source code is governed by a
4 // BSD-style license that can be found in the LICENSE file. 4 // BSD-style license that can be found in the LICENSE file.
5 // 5 //
6 // Modified by the Subzero authors. 6 // Modified by the Subzero authors.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // The Subzero Code Generator 10 // The Subzero Code Generator
(...skipping 3081 matching lines...) Expand 10 before | Expand all | Expand 10 after
3092 emitUint8(0x0F); 3092 emitUint8(0x0F);
3093 if (isByteSizedArithType(Ty)) 3093 if (isByteSizedArithType(Ty))
3094 emitUint8(0xC0); 3094 emitUint8(0xC0);
3095 else 3095 else
3096 emitUint8(0xC1); 3096 emitUint8(0xC1);
3097 emitOperand(gprEncoding(reg), addr); 3097 emitOperand(gprEncoding(reg), addr);
3098 } 3098 }
3099 3099
3100 template <class Machine> 3100 template <class Machine>
3101 void AssemblerX86Base<Machine>::xchg(Type Ty, 3101 void AssemblerX86Base<Machine>::xchg(Type Ty,
3102 typename Traits::GPRRegister reg0,
3103 typename Traits::GPRRegister reg1) {
3104 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
3105 if (Ty == IceType_i16)
3106 emitOperandSizeOverride();
3107 // Use short form if either register is EAX.
3108 if (reg0 == Traits::Encoded_Reg_Accumulator) {
3109 emitRexB(Ty, reg1);
3110 emitUint8(0x90 + reg1);
John 2015/08/12 17:44:57 emitUint8(0x90 + gprEncoding(reg1));
ascull 2015/08/17 22:18:52 Done.
3111 } else if (reg1 == Traits::Encoded_Reg_Accumulator) {
3112 emitRexB(Ty, reg0);
3113 emitUint8(0x90 + reg0);
John 2015/08/12 17:44:57 emitUint8(0x90 + gprEncoding(reg0));
ascull 2015/08/17 22:18:52 Done. Incl also only does `+ reg` is that a proble
3114 } else {
3115 emitRexRB(Ty, reg0, reg1);
3116 if (isByteSizedArithType(Ty))
3117 emitUint8(0x86);
3118 else
3119 emitUint8(0x87);
3120 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1));
3121 }
3122 }
3123
3124 template <class Machine>
3125 void AssemblerX86Base<Machine>::xchg(Type Ty,
3102 const typename Traits::Address &addr, 3126 const typename Traits::Address &addr,
3103 typename Traits::GPRRegister reg) { 3127 typename Traits::GPRRegister reg) {
3104 AssemblerBuffer::EnsureCapacity ensured(&Buffer); 3128 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
3105 if (Ty == IceType_i16) 3129 if (Ty == IceType_i16)
3106 emitOperandSizeOverride(); 3130 emitOperandSizeOverride();
3107 emitRex(Ty, addr, reg); 3131 emitRex(Ty, addr, reg);
3108 if (isByteSizedArithType(Ty)) 3132 if (isByteSizedArithType(Ty))
3109 emitUint8(0x86); 3133 emitUint8(0x86);
3110 else 3134 else
3111 emitUint8(0x87); 3135 emitUint8(0x87);
(...skipping 207 matching lines...) Expand 10 before | Expand all | Expand 10 after
3319 (void)shifter; 3343 (void)shifter;
3320 if (Ty == IceType_i16) 3344 if (Ty == IceType_i16)
3321 emitOperandSizeOverride(); 3345 emitOperandSizeOverride();
3322 emitRexB(Ty, operand.rm()); 3346 emitRexB(Ty, operand.rm());
3323 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); 3347 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3);
3324 emitOperand(rm, operand); 3348 emitOperand(rm, operand);
3325 } 3349 }
3326 3350
3327 } // end of namespace X86Internal 3351 } // end of namespace X86Internal
3328 } // end of namespace Ice 3352 } // end of namespace Ice
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