Subzero. Buildable, non-functional TargetLoweringX8664.

src/IceTargetLoweringX8664.h

Index: src/IceTargetLoweringX8664.h
diff --git a/src/IceTargetLoweringX8664.h b/src/IceTargetLoweringX8664.h
index 791343ac482a442d6b206513d52e1f35d25ae066..d145b491176ecf059f4805303f0fa8cf0214fc4a 100644
--- a/src/IceTargetLoweringX8664.h
+++ b/src/IceTargetLoweringX8664.h
@@ -16,22 +16,50 @@
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX8664_H
 
+#include "IceAssemblerX8664.h"
 #include "IceCfg.h"
 #include "IceGlobalContext.h"
+#include "IceInstX8664.h"
 #include "IceTargetLowering.h"
+#include "IceTargetLoweringX8664Traits.h"
+#include "IceTargetLoweringX86Base.h"
 
 namespace Ice {
 
-class TargetX8664 : public TargetLowering {
+class TargetX8664 final
+    : public ::Ice::X86Internal::TargetX86Base<TargetX8664> {
   TargetX8664() = delete;
   TargetX8664(const TargetX8664 &) = delete;
   TargetX8664 &operator=(const TargetX8664 &) = delete;
 
 public:
-  static TargetX8664 *create(Cfg *Func);
+  static TargetX8664 *create(Cfg *Func) { return new TargetX8664(Func); }
 
 private:
-  explicit TargetX8664(Cfg *Func) : TargetLowering(Func) {}
+  friend class ::Ice::X86Internal::TargetX86Base<TargetX8664>;
+
+  explicit TargetX8664(Cfg *Func)
+      : ::Ice::X86Internal::TargetX86Base<TargetX8664>(Func) {}
+
+  Operand *createNaClReadTPSrcOperand() {
+    Variable *TDB = callNaClReadTp();
+    Variable *RZP = materializeRZP();
+    Constant *TPOffset = Ctx->getConstantInt8(0x20);

[jvoung (off chromium), 2015/07/30 21:16:22]

Hmm this magic offset doesn't seem particularly familiar. It's not just the
return value of calling nacl_read_tp? Then the bitcode decides on which offset
to use from there. The sandboxing of that pointer (+RZP) happens separately as
part of the load sandboxing, I thought.

E.g.,

  %tls_raw = call i8* @llvm.nacl.read.tp()
  %tls_raw.asint = ptrtoint i8* %tls_raw to i32
  %gep = add i32 %tls_raw.asint, -1184
  %gep.asptr = inttoptr i32 %gep to i32*
  %0 = load i32, i32* %gep.asptr, align 1, !dbg !9330
  %cmp = icmp ne i32 %0, 1, !dbg !9332
  %gep37 = add i32 %tls_raw.asint, -1168
  %gep37.asptr = inttoptr i32 %gep37 to i32*
  %1 = load i32, i32* %gep37.asptr, align 1

For slots at -1184 and -1168.

[John, 2015/07/31 21:05:54]

I got confused with the comments in

native_client/src/untrusted/nacl/tls_params.h

Done.

+    return Traits::X86OperandMem::create(Func, IceType_i32, RZP, TPOffset, TDB);
+  }
+
+  Variable *callNaClReadTp() {
+    Variable *TDB = makeReg(IceType_i32);
+    InstCall *Call = makeHelperCall(H_call_read_tp, TDB, 0);
+    lowerCall(Call);
+    return TDB;
+  }
+
+  Variable *materializeRZP() {
+    Variable *RZP = makeReg(IceType_i32, Traits::RegisterSet::Reg_r15d);

[jvoung (off chromium), 2015/07/30 21:16:22]

Should this use getPhysicalRegister() and RZP marked live in on function entry?
Also, RZP should be const throughout the function and not get allocated.

[John, 2015/07/31 21:05:54]

N/A anymore (this method was removed.)

As to RZP being constant, this is not a problem -- yet. In these CLs (there 4 or
5) I am not trying to have a correct x86-64 backend -- I am just moving code
from the 32 to the 64 bit backend, with some minimal changes. The bulk of the
(interesting) work (i.e., getting this code to run) is coming after I have all
things in place and can actually start testing the code it generates. What I
want to say is -- don't overthink about whether something is horribly wrong. It
probably is and will be fixed soon in a separate CL.

[jvoung (off chromium), 2015/07/31 21:21:05]

Okay sounds fine for this CL. Just raising awareness, in case it helps with
testing later =)

[John, 2015/07/31 21:29:06]

You are  awesome at finding things that will be painful to fix later for they
are small (but with huge implications.) I was just trying to take some of the
load off your back as these CLs are really meant to lay the "canvas" for the
actual x86-64 implementation. I am sorry if I came across as harsh or impolite.

+    Context.insert(InstFakeDef::create(Func, RZP));
+    return RZP;
+  }
 };
 
 class TargetDataX8664 : public TargetDataLowering {
@@ -55,6 +83,7 @@ private:
   ENABLE_MAKE_UNIQUE;
 
   explicit TargetDataX8664(GlobalContext *Ctx) : TargetDataLowering(Ctx) {}
+  template <typename T> static void emitConstantPool(GlobalContext *Ctx);
 };
 
 class TargetHeaderX8664 : public TargetHeaderLowering {