Adds MIPS instructions to simulator, assembler, disassembler

runtime/vm/assembler_mips_test.cc

Index: runtime/vm/assembler_mips_test.cc
===================================================================
--- runtime/vm/assembler_mips_test.cc	(revision 19730)
+++ runtime/vm/assembler_mips_test.cc	(working copy)
@@ -55,7 +55,7 @@
 
 ASSEMBLER_TEST_GENERATE(Addiu_overflow, assembler) {
   __ LoadImmediate(V0, 0x7fffffff);
-  __ addiu(V0, V0, Immediate(1));  // V0 is set on overflow
+  __ addiu(V0, V0, Immediate(1));  // V0 is modified on overflow.
   __ jr(RA);
 }
 
@@ -124,7 +124,7 @@
 
 
 ASSEMBLER_TEST_GENERATE(Clo, assembler) {
-  __ addi(R1, ZR, Immediate(0xffff));
+  __ addi(R1, ZR, Immediate(-1));
   __ clo(V0, R1);
   __ jr(RA);
 }
@@ -240,6 +240,115 @@
 }
 
 
+ASSEMBLER_TEST_GENERATE(Ext, assembler) {
+  __ LoadImmediate(R1, 0x000ff000);
+  __ ext(V0, R1, 13, 8);

[regis, 2013/03/11 17:31:11]

I would expect pos = 12, since the caller expects 0xff.

+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Ext, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(static_cast<int32_t>(0xff),

[Ivan Posva, 2013/03/11 17:29:04]

Try getting only a part of the set bits.

+            EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Ins, assembler) {
+  __ LoadImmediate(R1, 0x000000ff);
+  __ LoadImmediate(V0, 0x000000ff);
+  __ ins(V0, R1, 13, 8);

[regis, 2013/03/11 17:31:11]

12?

+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Ins, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(static_cast<int32_t>(0xff0ff),

[Ivan Posva, 2013/03/11 17:29:04]

How about two different values in R1 and V0? Otherwise you will not notice if
you use the wrong source register.

+            EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Lb, assembler) {
+  __ addiu(SP, SP, Immediate(-kWordSize * 30));
+  __ LoadImmediate(R1, 0xff);
+  __ sb(R1, Immediate(0), SP);
+  __ lb(V0, Immediate(0), SP);
+  __ addiu(SP, SP, Immediate(kWordSize * 30));
+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Lb, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Lbu, assembler) {
+  __ addiu(SP, SP, Immediate(-kWordSize * 30));
+  __ LoadImmediate(R1, 0xff);
+  __ sb(R1, Immediate(0), SP);
+  __ lbu(V0, Immediate(0), SP);
+  __ addiu(SP, SP, Immediate(kWordSize * 30));
+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Lbu, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(255, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Lh, assembler) {
+  __ addiu(SP, SP, Immediate(-kWordSize * 30));
+  __ LoadImmediate(R1, 0xffff);
+  __ sh(R1, Immediate(0), SP);
+  __ lh(V0, Immediate(0), SP);
+  __ addiu(SP, SP, Immediate(kWordSize * 30));
+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Lh, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Lhu, assembler) {
+  __ addiu(SP, SP, Immediate(-kWordSize * 30));
+  __ LoadImmediate(R1, 0xffff);
+  __ sh(R1, Immediate(0), SP);
+  __ lhu(V0, Immediate(0), SP);
+  __ addiu(SP, SP, Immediate(kWordSize * 30));
+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Lhu, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(65535, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Lw, assembler) {
+  __ addiu(SP, SP, Immediate(-kWordSize * 30));
+  __ LoadImmediate(R1, -1);
+  __ sw(R1, Immediate(0), SP);
+  __ lw(V0, Immediate(0), SP);
+  __ addiu(SP, SP, Immediate(kWordSize * 30));
+  __ jr(RA);
+}
+
+
+ASSEMBLER_TEST_RUN(Lw, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
+}
+
+
 ASSEMBLER_TEST_GENERATE(Lui, assembler) {
   __ lui(V0, Immediate(0x2a));
   __ jr(RA);