Adds MIPS instructions to simulator, assembler, disassembler

runtime/vm/disassembler_mips.cc

Index: runtime/vm/disassembler_mips.cc
===================================================================
--- runtime/vm/disassembler_mips.cc	(revision 19730)
+++ runtime/vm/disassembler_mips.cc	(working copy)
@@ -37,6 +37,7 @@
 
   void DecodeSpecial(Instr* instr);
   void DecodeSpecial2(Instr* instr);
+  void DecodeSpecial3(Instr* instr);
 
   // Convenience functions.
   char* get_buffer() const { return buffer_; }
@@ -176,6 +177,7 @@
 
 
 void MIPSDecoder::DecodeSpecial(Instr* instr) {
+  ASSERT(instr->OpcodeField() == SPECIAL);
   switch (instr->FunctionField()) {
     case ADDU: {
       Format(instr, "addu 'rd, 'rs, 'rt");
@@ -227,6 +229,7 @@
 
 
 void MIPSDecoder::DecodeSpecial2(Instr* instr) {
+  ASSERT(instr->OpcodeField() == SPECIAL2);
   switch (instr->FunctionField()) {
     case CLO: {
       Format(instr, "clo 'rd, 'rs");
@@ -245,6 +248,26 @@
 }
 
 
+void MIPSDecoder::DecodeSpecial3(Instr* instr) {
+  ASSERT(instr->OpcodeField() == SPECIAL3);
+  switch (instr->FunctionField()) {
+    case EXT: {
+      Format(instr, "ext 'rt, 'rs, 'sa, 'rd");

[Ivan Posva, 2013/03/11 17:29:04]

'rd is certainly incorrect here. It will print the register and not the size.
Additionally you need to do some math on the values to map them back to pos and
size from their encoding. I suggest you create a new format option for this,
such as 'pos.

+      break;
+    }
+    case INS: {
+      Format(instr, "ins 'rt, 'rs, 'sa, 'rd");

[Ivan Posva, 2013/03/11 17:29:04]

ditto

+      break;
+    }
+    default: {
+      OS::PrintErr("DecodeSpecial3: 0x%x\n", instr->InstructionBits());
+      UNREACHABLE();
+      break;
+    }
+  }
+}
+
+
 void MIPSDecoder::InstructionDecode(Instr* instr) {
   switch (instr->OpcodeField()) {
     case SPECIAL: {
@@ -255,26 +278,58 @@
       DecodeSpecial2(instr);
       break;
     }
+    case SPECIAL3: {
+      DecodeSpecial3(instr);
+      break;
+    }
     case ADDI: {
-      Format(instr, "addi 'rt, 'rs, 'immu");
+      Format(instr, "addi 'rt, 'rs, 'imms");
       break;
     }
     case ADDIU: {
-      Format(instr, "addiu 'rt, 'rs, 'immu");
+      Format(instr, "addiu 'rt, 'rs, 'imms");
       break;
     }
     case ANDI: {
       Format(instr, "andi 'rt, 'rs, 'immu");
       break;
     }
+    case LB: {
+      Format(instr, "lb 'rt, 'imms('rs)");
+      break;
+    }
+    case LBU: {
+      Format(instr, "lbu 'rt, 'imms('rs)");
+      break;
+    }
+    case LH: {
+      Format(instr, "lh 'rt, 'imms('rs)");
+      break;
+    }
     case LUI: {
       Format(instr, "lui 'rt, 'immu");
       break;
     }
+    case LW: {
+      Format(instr, "lw 'rt, 'imms('rs)");
+      break;
+    }
     case ORI: {
       Format(instr, "ori 'rt, 'rs, 'immu");
       break;
     }
+    case SB: {
+      Format(instr, "sb 'rt, 'imms('rs)");
+      break;
+    }
+    case SH: {
+      Format(instr, "sh 'rt, 'imms('rs)");
+      break;
+    }
+    case SW: {
+      Format(instr, "sw 'rt, 'imms('rs)");
+      break;
+    }
     default: {
       OS::PrintErr("Undecoded instruction: 0x%x\n", instr->InstructionBits());
       UNREACHABLE();