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Unified Diff: src/compiler/mips64/code-generator-mips64.cc

Issue 1242303005: [turbofan]: Elide extra move when accessing stack or frame register (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: src/compiler/code-generator.cc Created 5 years, 5 months ago
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Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 77c9edf80d96e85fc24d5ccaeb741181af737e8c..fcd29137dcbba175ac425951efc47817945ebdb5 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -80,7 +80,7 @@ class MipsOperandConverter final : public InstructionOperandConverter {
Operand InputOperand(size_t index) {
InstructionOperand* op = instr_->InputAt(index);
- if (op->IsRegister()) {
+ if (op->GeneratesRegister()) {
return Operand(ToRegister(op));
}
return InputImmediate(index);
@@ -106,7 +106,7 @@ class MipsOperandConverter final : public InstructionOperandConverter {
MemOperand ToMemOperand(InstructionOperand* op) const {
DCHECK(op != NULL);
- DCHECK(!op->IsRegister());
+ DCHECK(!op->GeneratesRegister());
DCHECK(!op->IsDoubleRegister());
DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot());
// The linkage computes where all spill slots are located.
@@ -118,7 +118,7 @@ class MipsOperandConverter final : public InstructionOperandConverter {
static inline bool HasRegisterInput(Instruction* instr, size_t index) {
- return instr->InputAt(index)->IsRegister();
+ return instr->InputAt(index)->GeneratesRegister();
}
@@ -304,7 +304,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
do { \
auto result = i.Output##width##Register(); \
auto ool = new (zone()) OutOfLineLoad##width(this, result); \
- if (instr->InputAt(0)->IsRegister()) { \
+ if (instr->InputAt(0)->GeneratesRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ Daddu(at, i.InputRegister(2), offset); \
@@ -322,7 +322,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
do { \
auto result = i.OutputRegister(); \
auto ool = new (zone()) OutOfLineLoadInteger(this, result); \
- if (instr->InputAt(0)->IsRegister()) { \
+ if (instr->InputAt(0)->GeneratesRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ Daddu(at, i.InputRegister(2), offset); \
@@ -339,7 +339,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
#define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr) \
do { \
Label done; \
- if (instr->InputAt(0)->IsRegister()) { \
+ if (instr->InputAt(0)->GeneratesRegister()) { \
auto offset = i.InputRegister(0); \
auto value = i.Input##width##Register(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
@@ -358,7 +358,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
#define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \
do { \
Label done; \
- if (instr->InputAt(0)->IsRegister()) { \
+ if (instr->InputAt(0)->GeneratesRegister()) { \
auto offset = i.InputRegister(0); \
auto value = i.InputRegister(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
@@ -568,7 +568,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ Clz(i.OutputRegister(), i.InputRegister(0));
break;
case kMips64Shl:
- if (instr->InputAt(1)->IsRegister()) {
+ if (instr->InputAt(1)->GeneratesRegister()) {
__ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
@@ -577,7 +577,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
}
break;
case kMips64Shr:
- if (instr->InputAt(1)->IsRegister()) {
+ if (instr->InputAt(1)->GeneratesRegister()) {
__ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
@@ -586,7 +586,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
}
break;
case kMips64Sar:
- if (instr->InputAt(1)->IsRegister()) {
+ if (instr->InputAt(1)->GeneratesRegister()) {
__ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
@@ -603,7 +603,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
i.InputInt8(2));
break;
case kMips64Dshl:
- if (instr->InputAt(1)->IsRegister()) {
+ if (instr->InputAt(1)->GeneratesRegister()) {
__ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
@@ -617,7 +617,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
}
break;
case kMips64Dshr:
- if (instr->InputAt(1)->IsRegister()) {
+ if (instr->InputAt(1)->GeneratesRegister()) {
__ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
@@ -631,7 +631,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
}
break;
case kMips64Dsar:
- if (instr->InputAt(1)->IsRegister()) {
+ if (instr->InputAt(1)->GeneratesRegister()) {
__ dsrav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
@@ -1250,18 +1250,18 @@ void CodeGenerator::AssembleMove(InstructionOperand* source,
MipsOperandConverter g(this, NULL);
// Dispatch on the source and destination operand kinds. Not all
// combinations are possible.
- if (source->IsRegister()) {
- DCHECK(destination->IsRegister() || destination->IsStackSlot());
+ if (source->GeneratesRegister()) {
+ DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
Register src = g.ToRegister(source);
- if (destination->IsRegister()) {
+ if (destination->GeneratesRegister()) {
__ mov(g.ToRegister(destination), src);
} else {
__ sd(src, g.ToMemOperand(destination));
}
} else if (source->IsStackSlot()) {
- DCHECK(destination->IsRegister() || destination->IsStackSlot());
+ DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
MemOperand src = g.ToMemOperand(source);
- if (destination->IsRegister()) {
+ if (destination->GeneratesRegister()) {
__ ld(g.ToRegister(destination), src);
} else {
Register temp = kScratchReg;
@@ -1270,9 +1270,10 @@ void CodeGenerator::AssembleMove(InstructionOperand* source,
}
} else if (source->IsConstant()) {
Constant src = g.ToConstant(source);
- if (destination->IsRegister() || destination->IsStackSlot()) {
- Register dst =
- destination->IsRegister() ? g.ToRegister(destination) : kScratchReg;
+ if (destination->GeneratesRegister() || destination->IsStackSlot()) {
+ Register dst = destination->GeneratesRegister()
+ ? g.ToRegister(destination)
+ : kScratchReg;
switch (src.type()) {
case Constant::kInt32:
__ li(dst, Operand(src.ToInt32()));
@@ -1356,11 +1357,11 @@ void CodeGenerator::AssembleSwap(InstructionOperand* source,
MipsOperandConverter g(this, NULL);
// Dispatch on the source and destination operand kinds. Not all
// combinations are possible.
- if (source->IsRegister()) {
+ if (source->GeneratesRegister()) {
// Register-register.
Register temp = kScratchReg;
Register src = g.ToRegister(source);
- if (destination->IsRegister()) {
+ if (destination->GeneratesRegister()) {
Register dst = g.ToRegister(destination);
__ Move(temp, src);
__ Move(src, dst);
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