Adds vstm, vldm to ARM simulator, assembler, disassembler

runtime/vm/disassembler_arm.cc

Index: runtime/vm/disassembler_arm.cc
===================================================================
--- runtime/vm/disassembler_arm.cc	(revision 19322)
+++ runtime/vm/disassembler_arm.cc	(working copy)
@@ -296,6 +296,19 @@
       PrintSRegister(reg);
       return 2;
     }
+  } else if (format[1] == 'l') {
+    ASSERT(STRING_STARTS_WITH(format, "slist"));
+    int regs = instr->Bits(0, 8);

[regis, 2013/03/04 17:25:40]

reg_count?

+    int start = instr->Bit(22) | (instr->Bits(12, 4) << 1);
+    Print("{");
+    for (int i = start; i < start + regs; i++) {
+      PrintSRegister(i);
+      if (i != start + regs - 1) {
+        Print(", ");
+      }
+    }
+    Print("}");
+    return 5;
   }
   UNREACHABLE();
   return -1;
@@ -316,6 +329,19 @@
     int reg = instr->DmField();
     PrintDRegister(reg);
     return 2;
+  } else if (format[1] == 'l') {
+    ASSERT(STRING_STARTS_WITH(format, "dlist"));
+    int regs = instr->Bits(0, 8) >> 1;
+    int start = (instr->Bit(22) << 4) | instr->Bits(12, 4);
+    Print("{");
+    for (int i = start; i < start + regs; i++) {
+      PrintDRegister(i);
+      if (i != start + regs - 1) {
+        Print(", ");
+      }
+    }
+    Print("}");
+    return 5;
   }
   UNREACHABLE();
   return -1;
@@ -920,6 +946,20 @@
         }
       }
     }
+  } else if (instr->IsVFPMultipleLoadStore()) {
+    if (instr->HasL()) {  // vldm
+      if (instr->Bit(8)) {  // vldmd
+        Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
+      } else {  // vldms
+        Format(instr, "vldms'cond'pu 'rn'w, 'slist");
+      }
+    } else {  // vstm
+      if (instr->Bit(8)) {  // vstmd
+        Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
+      } else {  // vstms
+        Format(instr, "vstms'cond'pu 'rn'w, 'slist");
+      }
+    }
   } else {
     Unknown(instr);
   }