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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/disassembler.h" | 5 #include "vm/disassembler.h" |
| 6 | 6 |
| 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. | 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. |
| 8 #if defined(TARGET_ARCH_ARM) | 8 #if defined(TARGET_ARCH_ARM) |
| 9 #include "platform/assert.h" | 9 #include "platform/assert.h" |
| 10 | 10 |
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| 289 int reg = instr->SmField(); | 289 int reg = instr->SmField(); |
| 290 if (format[2] == '1') { // 'sm1: S[m+1] register | 290 if (format[2] == '1') { // 'sm1: S[m+1] register |
| 291 reg++; | 291 reg++; |
| 292 ASSERT(reg < kNumberOfSRegisters); | 292 ASSERT(reg < kNumberOfSRegisters); |
| 293 PrintSRegister(reg); | 293 PrintSRegister(reg); |
| 294 return 3; | 294 return 3; |
| 295 } else { // 'sm: Sm register | 295 } else { // 'sm: Sm register |
| 296 PrintSRegister(reg); | 296 PrintSRegister(reg); |
| 297 return 2; | 297 return 2; |
| 298 } | 298 } |
| 299 } else if (format[1] == 'l') { | |
| 300 ASSERT(STRING_STARTS_WITH(format, "slist")); | |
| 301 int regs = instr->Bits(0, 8); | |
|
regis
2013/03/04 17:25:40
reg_count?
| |
| 302 int start = instr->Bit(22) | (instr->Bits(12, 4) << 1); | |
| 303 Print("{"); | |
| 304 for (int i = start; i < start + regs; i++) { | |
| 305 PrintSRegister(i); | |
| 306 if (i != start + regs - 1) { | |
| 307 Print(", "); | |
| 308 } | |
| 309 } | |
| 310 Print("}"); | |
| 311 return 5; | |
| 299 } | 312 } |
| 300 UNREACHABLE(); | 313 UNREACHABLE(); |
| 301 return -1; | 314 return -1; |
| 302 } | 315 } |
| 303 | 316 |
| 304 | 317 |
| 305 int ARMDecoder::FormatDRegister(Instr* instr, const char* format) { | 318 int ARMDecoder::FormatDRegister(Instr* instr, const char* format) { |
| 306 ASSERT(format[0] == 'd'); | 319 ASSERT(format[0] == 'd'); |
| 307 if (format[1] == 'n') { // 'dn: Dn register | 320 if (format[1] == 'n') { // 'dn: Dn register |
| 308 int reg = instr->DnField(); | 321 int reg = instr->DnField(); |
| 309 PrintDRegister(reg); | 322 PrintDRegister(reg); |
| 310 return 2; | 323 return 2; |
| 311 } else if (format[1] == 'd') { // 'dd: Dd register | 324 } else if (format[1] == 'd') { // 'dd: Dd register |
| 312 int reg = instr->DdField(); | 325 int reg = instr->DdField(); |
| 313 PrintDRegister(reg); | 326 PrintDRegister(reg); |
| 314 return 2; | 327 return 2; |
| 315 } else if (format[1] == 'm') { // 'dm: Dm register | 328 } else if (format[1] == 'm') { // 'dm: Dm register |
| 316 int reg = instr->DmField(); | 329 int reg = instr->DmField(); |
| 317 PrintDRegister(reg); | 330 PrintDRegister(reg); |
| 318 return 2; | 331 return 2; |
| 332 } else if (format[1] == 'l') { | |
| 333 ASSERT(STRING_STARTS_WITH(format, "dlist")); | |
| 334 int regs = instr->Bits(0, 8) >> 1; | |
| 335 int start = (instr->Bit(22) << 4) | instr->Bits(12, 4); | |
| 336 Print("{"); | |
| 337 for (int i = start; i < start + regs; i++) { | |
| 338 PrintDRegister(i); | |
| 339 if (i != start + regs - 1) { | |
| 340 Print(", "); | |
| 341 } | |
| 342 } | |
| 343 Print("}"); | |
| 344 return 5; | |
| 319 } | 345 } |
| 320 UNREACHABLE(); | 346 UNREACHABLE(); |
| 321 return -1; | 347 return -1; |
| 322 } | 348 } |
| 323 | 349 |
| 324 | 350 |
| 325 // FormatOption takes a formatting string and interprets it based on | 351 // FormatOption takes a formatting string and interprets it based on |
| 326 // the current instructions. The format string points to the first | 352 // the current instructions. The format string points to the first |
| 327 // character of the option string (the option escape has already been | 353 // character of the option string (the option escape has already been |
| 328 // consumed by the caller.) FormatOption returns the number of | 354 // consumed by the caller.) FormatOption returns the number of |
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| 913 Format(instr, "vldrd'cond 'dd, ['rn, #-'off10]"); | 939 Format(instr, "vldrd'cond 'dd, ['rn, #-'off10]"); |
| 914 } | 940 } |
| 915 } else { // vstrd | 941 } else { // vstrd |
| 916 if (instr->Bit(23) == 1) { | 942 if (instr->Bit(23) == 1) { |
| 917 Format(instr, "vstrd'cond 'dd, ['rn, #+'off10]"); | 943 Format(instr, "vstrd'cond 'dd, ['rn, #+'off10]"); |
| 918 } else { | 944 } else { |
| 919 Format(instr, "vstrd'cond 'dd, ['rn, #-'off10]"); | 945 Format(instr, "vstrd'cond 'dd, ['rn, #-'off10]"); |
| 920 } | 946 } |
| 921 } | 947 } |
| 922 } | 948 } |
| 949 } else if (instr->IsVFPMultipleLoadStore()) { | |
| 950 if (instr->HasL()) { // vldm | |
| 951 if (instr->Bit(8)) { // vldmd | |
| 952 Format(instr, "vldmd'cond'pu 'rn'w, 'dlist"); | |
| 953 } else { // vldms | |
| 954 Format(instr, "vldms'cond'pu 'rn'w, 'slist"); | |
| 955 } | |
| 956 } else { // vstm | |
| 957 if (instr->Bit(8)) { // vstmd | |
| 958 Format(instr, "vstmd'cond'pu 'rn'w, 'dlist"); | |
| 959 } else { // vstms | |
| 960 Format(instr, "vstms'cond'pu 'rn'w, 'slist"); | |
| 961 } | |
| 962 } | |
| 923 } else { | 963 } else { |
| 924 Unknown(instr); | 964 Unknown(instr); |
| 925 } | 965 } |
| 926 } | 966 } |
| 927 | 967 |
| 928 | 968 |
| 929 void ARMDecoder::DecodeType7(Instr* instr) { | 969 void ARMDecoder::DecodeType7(Instr* instr) { |
| 930 if (instr->Bit(24) == 1) { | 970 if (instr->Bit(24) == 1) { |
| 931 Format(instr, "svc'cond #'svc"); | 971 Format(instr, "svc'cond #'svc"); |
| 932 if (instr->SvcField() == kStopMessageSvcCode) { | 972 if (instr->SvcField() == kStopMessageSvcCode) { |
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| 1245 human_buffer, | 1285 human_buffer, |
| 1246 sizeof(human_buffer), | 1286 sizeof(human_buffer), |
| 1247 pc); | 1287 pc); |
| 1248 pc += instruction_length; | 1288 pc += instruction_length; |
| 1249 } | 1289 } |
| 1250 } | 1290 } |
| 1251 | 1291 |
| 1252 } // namespace dart | 1292 } // namespace dart |
| 1253 | 1293 |
| 1254 #endif // defined TARGET_ARCH_ARM | 1294 #endif // defined TARGET_ARCH_ARM |
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