Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(564)

Unified Diff: runtime/vm/assembler_arm_test.cc

Issue 12378080: Adds mrc instruction to arm simulator, assembler, disassembler. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « runtime/vm/assembler_arm.cc ('k') | runtime/vm/constants_arm.h » ('j') | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: runtime/vm/assembler_arm_test.cc
===================================================================
--- runtime/vm/assembler_arm_test.cc (revision 19404)
+++ runtime/vm/assembler_arm_test.cc (working copy)
@@ -1361,6 +1361,68 @@
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
}
+
+// Check that assembler mrc instruction encoding, and simulator decoding
+// are in agreement.
+#if defined(USING_SIMULATOR)
+ASSEMBLER_TEST_GENERATE(MrcHaveDiv, assembler) {
+ __ mrc(R0, 15, 0, 0, 2, 0);
+ __ Lsr(R0, R0, 24);
+ __ and_(R0, R0, ShifterOperand(0xf));
+ __ mov(PC, ShifterOperand(LR));
+}
+
+
+ASSEMBLER_TEST_RUN(MrcHaveDiv, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ bool b = CPUFeatures::integer_division_supported();
+ CPUFeatures::set_integer_division_supported(true);
+ EXPECT_LT(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+ CPUFeatures::set_integer_division_supported(b);
+}
+
+
+ASSEMBLER_TEST_GENERATE(MrcNoDiv, assembler) {
+ __ mrc(R0, 15, 0, 0, 2, 0);
+ __ Lsr(R0, R0, 24);
+ __ and_(R0, R0, ShifterOperand(0xf));
+ __ mov(PC, ShifterOperand(LR));
+}
+
+
+ASSEMBLER_TEST_RUN(MrcNoDiv, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ bool b = CPUFeatures::integer_division_supported();
+ CPUFeatures::set_integer_division_supported(false);
+ EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+ CPUFeatures::set_integer_division_supported(b);
+}
+#endif // defined(USING_SIMULATOR)
+
+
+ASSEMBLER_TEST_GENERATE(MrcReal, assembler) {
+ __ mrc(R0, 15, 0, 0, 2, 0);
+ __ Lsr(R0, R0, 24);
+ __ and_(R0, R0, ShifterOperand(0xf));
+ __ mov(PC, ShifterOperand(LR));
+}
+
+
+ASSEMBLER_TEST_RUN(MrcReal, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ bool have_div = CPUFeatures::integer_division_supported();
+ int32_t r = EXECUTE_TEST_CODE_INT32(Tst, test->entry());
+ if (have_div) {
+ EXPECT_LT(0, r);
+ } else {
+ EXPECT_EQ(0, r);
+ }
+}
+
+
} // namespace dart
#endif // defined TARGET_ARCH_ARM
« no previous file with comments | « runtime/vm/assembler_arm.cc ('k') | runtime/vm/constants_arm.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698