src/trusted/validator_arm/gen/arm32_decode_actuals_1.h - Issue 12223046: Use generated actual decoders for ARM table:

Unified Diff: src/trusted/validator_arm/gen/arm32_decode_actuals_1.h

Issue 12223046: Use generated actual decoders for ARM table: (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/

Patch Set: Created 7 years, 10 months ago

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Index: src/trusted/validator_arm/gen/arm32_decode_actuals_1.h

===================================================================

--- src/trusted/validator_arm/gen/arm32_decode_actuals_1.h (revision 10760)

+++ src/trusted/validator_arm/gen/arm32_decode_actuals_1.h (working copy)

@@ -1945,7 +1945,7 @@

// Actual:

// {defs: {15, 14},

// relative: true,

-// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32),

+// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32) + 8,

// safety: [true => MAY_BE_SAFE],

// uses: {15}}

@@ -1953,6 +1953,7 @@

// {Cond: Cond(31:28),

// Lr: 14,

// Pc: 15,

+// actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc, Lr},

@@ -1962,7 +1963,7 @@

// imm32: SignExtend(imm24:'00'(1:0), 32),

// pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: BL_BLX_immediate,

// safety: [true => MAY_BE_SAFE],

// true: true,

@@ -1987,13 +1988,14 @@

// Actual:

// {defs: {15},

// relative: true,

-// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32),

+// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32) + 8,

// safety: [true => MAY_BE_SAFE],

// uses: {15}}

// Baseline:

// {Cond: Cond(31:28),

// Pc: 15,

+// actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc},

@@ -2003,7 +2005,7 @@

// imm32: SignExtend(imm24:'00'(1:0), 32),

// pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: B,

// safety: [true => MAY_BE_SAFE],

// true: true,

@@ -2808,7 +2810,7 @@

// Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS,

// inst(21)=1 &&

// Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN],

-// small_imm_base_wb: true,

+// small_imm_base_wb: inst(21)=1,

// uses: {inst(19:16)}}

// Baseline:

@@ -2816,6 +2818,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2836,8 +2839,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

@@ -2846,6 +2848,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2866,8 +2869,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

@@ -2876,6 +2878,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2896,8 +2899,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

@@ -2906,6 +2908,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2926,8 +2929,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1

@@ -6944,7 +6946,7 @@

// Contains(RegisterList(inst(15:0)), inst(19:16)) &&

// SmallestGPR(RegisterList(inst(15:0))) !=

// inst(19:16) => UNKNOWN],

-// small_imm_base_wb: true,

+// small_imm_base_wb: inst(21)=1,

// uses: Union({inst(19:16)}, RegisterList(inst(15:0)))}

// Baseline:

@@ -6952,6 +6954,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -6973,8 +6976,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

@@ -6983,6 +6985,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -7004,8 +7007,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

@@ -7014,6 +7016,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -7035,8 +7038,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

@@ -7045,6 +7047,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -7066,8 +7069,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1

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