src/trusted/validator_arm/gen/arm32_decode_actuals_1.h - Issue 12223046: Use generated actual decoders for ARM table:

Unified Diff: src/trusted/validator_arm/gen/arm32_decode_actuals_1.h

Issue 12223046: Use generated actual decoders for ARM table: (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/

Patch Set: Created 7 years, 10 months ago

Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.

Jump to:

View side-by-side diff with in-line comments

Download patch

« src/trusted/validator_arm/armv7.table ('K') | « src/trusted/validator_arm/gen/arm32_decode.cc ('k') | src/trusted/validator_arm/gen/arm32_decode_actuals_1.cc » ('j') | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Hide Comments ('s')

Index: src/trusted/validator_arm/gen/arm32_decode_actuals_1.h

===================================================================

--- src/trusted/validator_arm/gen/arm32_decode_actuals_1.h (revision 10736)

+++ src/trusted/validator_arm/gen/arm32_decode_actuals_1.h (working copy)

@@ -1943,7 +1943,7 @@

// Actual:

// {defs: {15, 14},

// relative: true,

-// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32),

+// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32) + 8,

// safety: [true => MAY_BE_SAFE],

// uses: {15}}

@@ -1951,6 +1951,7 @@

// {Cond: Cond(31:28),

// Lr: 14,

// Pc: 15,

+// actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc, Lr},

@@ -1960,7 +1961,7 @@

// imm32: SignExtend(imm24:'00'(1:0), 32),

// pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: BL_BLX_immediate,

// safety: [true => MAY_BE_SAFE],

// true: true,

@@ -1985,13 +1986,14 @@

// Actual:

// {defs: {15},

// relative: true,

-// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32),

+// relative_offset: SignExtend(inst(23:0):'00'(1:0), 32) + 8,

// safety: [true => MAY_BE_SAFE],

// uses: {15}}

// Baseline:

// {Cond: Cond(31:28),

// Pc: 15,

+// actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc},

@@ -2001,7 +2003,7 @@

// imm32: SignExtend(imm24:'00'(1:0), 32),

// pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: B,

// safety: [true => MAY_BE_SAFE],

// true: true,

@@ -2792,7 +2794,7 @@

// Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS,

// inst(21)=1 &&

// Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN],

-// small_imm_base_wb: true,

+// small_imm_base_wb: inst(21)=1,

// uses: {inst(19:16)}}

// Baseline:

@@ -2800,6 +2802,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2820,8 +2823,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

@@ -2830,6 +2832,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2850,8 +2853,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

@@ -2860,6 +2862,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2880,8 +2883,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

@@ -2890,6 +2892,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// cond: cond(31:28),

@@ -2910,8 +2913,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1

@@ -6867,7 +6869,7 @@

// Contains(RegisterList(inst(15:0)), inst(19:16)) &&

// SmallestGPR(RegisterList(inst(15:0))) !=

// inst(19:16) => UNKNOWN],

-// small_imm_base_wb: true,

+// small_imm_base_wb: inst(21)=1,

// uses: Union({inst(19:16)}, RegisterList(inst(15:0)))}

// Baseline:

@@ -6875,6 +6877,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -6896,8 +6899,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

@@ -6906,6 +6908,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -6927,8 +6930,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

@@ -6937,6 +6939,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -6958,8 +6961,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

@@ -6968,6 +6970,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// cond: cond(31:28),

@@ -6989,8 +6992,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1