Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_baselines_2.h

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_2_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_2_H_
@@ skipping 527 matching lines @@
   NACL_DISALLOW_COPY_AND_ASSIGN(
       STC_cccc110pudw0nnnnddddcccciiiiiiii_case_0);
 };
 
 // STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100000w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STMDA_STMED,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 class STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual bool base_address_register_writeback_small_immediate(
       Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0);
 };
 
 // STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100100w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STMDB_STMFD,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 class STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual bool base_address_register_writeback_small_immediate(
       Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0);
 };
 
 // STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100110w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STMIB_STMFA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 class STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual bool base_address_register_writeback_small_immediate(
       Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0);
 };
 
 // STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100010w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STM_STMIA_STMEA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 class STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
@@ skipping 5690 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       VHSUB_1111001u0dssnnnndddd0010nqm0mmmm_case_0);
 };
 
 } // namespace nacl_arm_test
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_2_H_