Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_baselines_1.cc

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_baselines.h"
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 1405 matching lines @@
   // uses: '{inst(3:0)}'
   return RegisterList().
    Add(Register((inst.Bits() & 0x0000000F)));
 }
 
 // BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0:
 //
 //   {Cond: Cond(31:28),
 //    Lr: 14,
 //    Pc: 15,
+//    actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,
 //    baseline: BranchImmediate24,
 //    constraints: ,
 //    defs: {Pc, Lr},
 //    fields: [Cond(31:28), imm24(23:0)],
 //    generated_baseline: BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0,
 //    imm24: imm24(23:0),
 //    imm32: SignExtend(imm24:'00'(1:0), 32),
 //    pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,
 //    relative: true,
-//    relative_offset: imm32,
+//    relative_offset: imm32 + 8,
 //    rule: BL_BLX_immediate,
 //    safety: [true => MAY_BE_SAFE],
 //    true: true,
 //    uses: {Pc}}
 RegisterList BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 defs(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // defs: '{15, 14}'
   return RegisterList().
    Add(Register(15)).
    Add(Register(14));
 }
 
 bool BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 is_relative_branch(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // relative: 'true'
   return true;
 }
 
 int32_t BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 branch_target_offset(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32)"
+  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32) + 8"
   return (((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) & 0x02000000)
        ? ((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) | 0xFC000000)
-       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003)));
+       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) + 8;
 }
 
 SafetyLevel BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // true => MAY_BE_SAFE
   if (true)
     return MAY_BE_SAFE;
 
   return MAY_BE_SAFE;
 }
 
 
 RegisterList BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{15}'
   return RegisterList().
    Add(Register(15));
 }
 
 // B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0:
 //
 //   {Cond: Cond(31:28),
 //    Pc: 15,
+//    actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,
 //    baseline: BranchImmediate24,
 //    constraints: ,
 //    defs: {Pc},
 //    fields: [Cond(31:28), imm24(23:0)],
 //    generated_baseline: B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0,
 //    imm24: imm24(23:0),
 //    imm32: SignExtend(imm24:'00'(1:0), 32),
 //    pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,
 //    relative: true,
-//    relative_offset: imm32,
+//    relative_offset: imm32 + 8,
 //    rule: B,
 //    safety: [true => MAY_BE_SAFE],
 //    true: true,
 //    uses: {Pc}}
 RegisterList B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 defs(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // defs: '{15}'
   return RegisterList().
    Add(Register(15));
 }
 
 bool B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 is_relative_branch(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // relative: 'true'
   return true;
 }
 
 int32_t B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 branch_target_offset(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32)"
+  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32) + 8"
   return (((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) & 0x02000000)
        ? ((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) | 0xFC000000)
-       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003)));
+       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) + 8;
 }
 
 SafetyLevel B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // true => MAY_BE_SAFE
   if (true)
     return MAY_BE_SAFE;
 
@@ skipping 1147 matching lines @@
   // uses: '{}'
   return RegisterList();
 }
 
 // LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100000w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDMDA_LDMFA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 Register LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 33 matching lines @@
     return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 
 bool LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{inst(19:16)}'
   return RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
 }
 
 // LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100100w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDMDB_LDMEA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 Register LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 33 matching lines @@
     return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 
 bool LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{inst(19:16)}'
   return RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
 }
 
 // LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100110w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDMIB_LDMED,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 Register LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 33 matching lines @@
     return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 
 bool LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{inst(19:16)}'
   return RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
 }
 
 // LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100010w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDM_LDMIA_LDMFD,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 Register LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 33 matching lines @@
     return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 
 bool LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{inst(19:16)}'
   return RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
 }
 
@@ skipping 7708 matching lines @@
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{inst(19:16), inst(15:12), inst(11:8), inst(3:0)}'
   return RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
    Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
    Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
    Add(Register((inst.Bits() & 0x0000000F)));
 }
 
 }  // namespace nacl_arm_dec