| OLD | NEW |
| 1 /* | 1 /* |
| 2 * Copyright 2013 The Native Client Authors. All rights reserved. | 2 * Copyright 2013 The Native Client Authors. All rights reserved. |
| 3 * Use of this source code is governed by a BSD-style license that can | 3 * Use of this source code is governed by a BSD-style license that can |
| 4 * be found in the LICENSE file. | 4 * be found in the LICENSE file. |
| 5 */ | 5 */ |
| 6 | 6 |
| 7 // DO NOT EDIT: GENERATED CODE | 7 // DO NOT EDIT: GENERATED CODE |
| 8 | 8 |
| 9 | 9 |
| 10 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_ | 10 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_ |
| (...skipping 141 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 152 const Actual_ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_1 Actual_ADD_
immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_1_instance_; | 152 const Actual_ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_1 Actual_ADD_
immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_1_instance_; |
| 153 const Actual_ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_1 Actual_ADR_A1_cccc
001010001111ddddiiiiiiiiiiii_case_1_instance_; | 153 const Actual_ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_1 Actual_ADR_A1_cccc
001010001111ddddiiiiiiiiiiii_case_1_instance_; |
| 154 const Actual_ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_1 Actual_ASR_
immediate_cccc0001101s0000ddddiiiii100mmmm_case_1_instance_; | 154 const Actual_ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_1 Actual_ASR_
immediate_cccc0001101s0000ddddiiiii100mmmm_case_1_instance_; |
| 155 const Actual_ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_1 Actual_ASR_r
egister_cccc0001101s0000ddddmmmm0101nnnn_case_1_instance_; | 155 const Actual_ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_1 Actual_ASR_r
egister_cccc0001101s0000ddddmmmm0101nnnn_case_1_instance_; |
| 156 const Actual_BFC_cccc0111110mmmmmddddlllll0011111_case_1 Actual_BFC_cccc011111
0mmmmmddddlllll0011111_case_1_instance_; | 156 const Actual_BFC_cccc0111110mmmmmddddlllll0011111_case_1 Actual_BFC_cccc011111
0mmmmmddddlllll0011111_case_1_instance_; |
| 157 const Actual_BFI_cccc0111110mmmmmddddlllll001nnnn_case_1 Actual_BFI_cccc011111
0mmmmmddddlllll001nnnn_case_1_instance_; | 157 const Actual_BFI_cccc0111110mmmmmddddlllll001nnnn_case_1 Actual_BFI_cccc011111
0mmmmmddddlllll001nnnn_case_1_instance_; |
| 158 const Actual_BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_1 Actual_BIC_
immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_1_instance_; | 158 const Actual_BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_1 Actual_BIC_
immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_1_instance_; |
| 159 const Actual_BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_1 Actual_BKPT_cccc0001
0010iiiiiiiiiiii0111iiii_case_1_instance_; | 159 const Actual_BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_1 Actual_BKPT_cccc0001
0010iiiiiiiiiiii0111iiii_case_1_instance_; |
| 160 const Actual_BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_1 Actual_BLX_
immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_; | 160 const Actual_BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_1 Actual_BLX_
immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_; |
| 161 const Actual_BLX_register_cccc000100101111111111110011mmmm_case_1 Actual_BLX_r
egister_cccc000100101111111111110011mmmm_case_1_instance_; | 161 const Actual_BLX_register_cccc000100101111111111110011mmmm_case_1 Actual_BLX_r
egister_cccc000100101111111111110011mmmm_case_1_instance_; |
| 162 const Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1 Actual_B
L_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_; |
| 163 const Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1 Actual_B_cccc1010iiiiii
iiiiiiiiiiiiiiiiii_case_1_instance_; |
| 162 const Actual_Bx_cccc000100101111111111110001mmmm_case_1 Actual_Bx_cccc00010010
1111111111110001mmmm_case_1_instance_; | 164 const Actual_Bx_cccc000100101111111111110001mmmm_case_1 Actual_Bx_cccc00010010
1111111111110001mmmm_case_1_instance_; |
| 163 const Actual_CLZ_cccc000101101111dddd11110001mmmm_case_1 Actual_CLZ_cccc000101
101111dddd11110001mmmm_case_1_instance_; | 165 const Actual_CLZ_cccc000101101111dddd11110001mmmm_case_1 Actual_CLZ_cccc000101
101111dddd11110001mmmm_case_1_instance_; |
| 164 const Actual_CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_1 Actual_CMN_
immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_1_instance_; | 166 const Actual_CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_1 Actual_CMN_
immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_1_instance_; |
| 165 const Actual_CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_1 Actual_CMN_r
egister_cccc00010111nnnn0000iiiiitt0mmmm_case_1_instance_; | 167 const Actual_CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_1 Actual_CMN_r
egister_cccc00010111nnnn0000iiiiitt0mmmm_case_1_instance_; |
| 166 const Actual_CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_ca
se_1 Actual_CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_
1_instance_; | 168 const Actual_CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_ca
se_1 Actual_CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_
1_instance_; |
| 169 const Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1 Actual_LDMDA_
LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_instance_; |
| 167 const Actual_LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_1 Actual_LDR
B_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_1_instance_; | 170 const Actual_LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_1 Actual_LDR
B_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_1_instance_; |
| 168 const Actual_LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_1 Actual_LDRB_
literal_cccc0101u1011111ttttiiiiiiiiiiii_case_1_instance_; | 171 const Actual_LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_1 Actual_LDRB_
literal_cccc0101u1011111ttttiiiiiiiiiiii_case_1_instance_; |
| 169 const Actual_LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_1 Actual_LDRB
_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_1_instance_; | 172 const Actual_LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_1 Actual_LDRB
_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_1_instance_; |
| 170 const Actual_LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_1 Actual_LDR
D_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_1_instance_; | 173 const Actual_LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_1 Actual_LDR
D_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_1_instance_; |
| 171 const Actual_LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_1 Actual_LDRD_
literal_cccc0001u1001111ttttiiii1101iiii_case_1_instance_; | 174 const Actual_LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_1 Actual_LDRD_
literal_cccc0001u1001111ttttiiii1101iiii_case_1_instance_; |
| 172 const Actual_LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_1 Actual_LDRD
_register_cccc000pu0w0nnnntttt00001101mmmm_case_1_instance_; | 175 const Actual_LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_1 Actual_LDRD
_register_cccc000pu0w0nnnntttt00001101mmmm_case_1_instance_; |
| 173 const Actual_LDREXB_cccc00011101nnnntttt111110011111_case_1 Actual_LDREXB_cccc
00011101nnnntttt111110011111_case_1_instance_; | 176 const Actual_LDREXB_cccc00011101nnnntttt111110011111_case_1 Actual_LDREXB_cccc
00011101nnnntttt111110011111_case_1_instance_; |
| 174 const Actual_LDREXD_cccc00011011nnnntttt111110011111_case_1 Actual_LDREXD_cccc
00011011nnnntttt111110011111_case_1_instance_; | 177 const Actual_LDREXD_cccc00011011nnnntttt111110011111_case_1 Actual_LDREXD_cccc
00011011nnnntttt111110011111_case_1_instance_; |
| 175 const Actual_LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_1 Actual_LDR
H_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_1_instance_; | 178 const Actual_LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_1 Actual_LDR
H_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_1_instance_; |
| 176 const Actual_LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_1 Actual_LDRH_
literal_cccc000pu1w11111ttttiiii1011iiii_case_1_instance_; | 179 const Actual_LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_1 Actual_LDRH_
literal_cccc000pu1w11111ttttiiii1011iiii_case_1_instance_; |
| (...skipping 14 matching lines...) Expand all Loading... |
| 191 const Actual_ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_1 Actual_ORR_
immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_1_instance_; | 194 const Actual_ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_1 Actual_ORR_
immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_1_instance_; |
| 192 const Actual_PKH_cccc01101000nnnnddddiiiiit01mmmm_case_1 Actual_PKH_cccc011010
00nnnnddddiiiiit01mmmm_case_1_instance_; | 195 const Actual_PKH_cccc01101000nnnnddddiiiiit01mmmm_case_1 Actual_PKH_cccc011010
00nnnnddddiiiiit01mmmm_case_1_instance_; |
| 193 const Actual_SBFX_cccc0111101wwwwwddddlllll101nnnn_case_1 Actual_SBFX_cccc0111
101wwwwwddddlllll101nnnn_case_1_instance_; | 196 const Actual_SBFX_cccc0111101wwwwwddddlllll101nnnn_case_1 Actual_SBFX_cccc0111
101wwwwwddddlllll101nnnn_case_1_instance_; |
| 194 const Actual_SDIV_cccc01110001dddd1111mmmm0001nnnn_case_1 Actual_SDIV_cccc0111
0001dddd1111mmmm0001nnnn_case_1_instance_; | 197 const Actual_SDIV_cccc01110001dddd1111mmmm0001nnnn_case_1 Actual_SDIV_cccc0111
0001dddd1111mmmm0001nnnn_case_1_instance_; |
| 195 const Actual_SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_1 Actual_SMLAD_cccc01
110000ddddaaaammmm00m1nnnn_case_1_instance_; | 198 const Actual_SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_1 Actual_SMLAD_cccc01
110000ddddaaaammmm00m1nnnn_case_1_instance_; |
| 196 const Actual_SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_
case_1 Actual_SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_c
ase_1_instance_; | 199 const Actual_SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_
case_1 Actual_SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_c
ase_1_instance_; |
| 197 const Actual_SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_1 Actual_SMLALD_cccc
01110100hhhhllllmmmm00m1nnnn_case_1_instance_; | 200 const Actual_SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_1 Actual_SMLALD_cccc
01110100hhhhllllmmmm00m1nnnn_case_1_instance_; |
| 198 const Actual_SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_1 Actual_SMLAL_A1_
cccc0000111shhhhllllmmmm1001nnnn_case_1_instance_; | 201 const Actual_SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_1 Actual_SMLAL_A1_
cccc0000111shhhhllllmmmm1001nnnn_case_1_instance_; |
| 199 const Actual_SMULBB_SMULBT_SMULTB_SMULTT_cccc00010110dddd0000mmmm1xx0nnnn_case
_1 Actual_SMULBB_SMULBT_SMULTB_SMULTT_cccc00010110dddd0000mmmm1xx0nnnn_case_1_in
stance_; | 202 const Actual_SMULBB_SMULBT_SMULTB_SMULTT_cccc00010110dddd0000mmmm1xx0nnnn_case
_1 Actual_SMULBB_SMULBT_SMULTB_SMULTT_cccc00010110dddd0000mmmm1xx0nnnn_case_1_in
stance_; |
| 200 const Actual_SMULL_A1_cccc0000110shhhhllllmmmm1001nnnn_case_1 Actual_SMULL_A1_
cccc0000110shhhhllllmmmm1001nnnn_case_1_instance_; | 203 const Actual_SMULL_A1_cccc0000110shhhhllllmmmm1001nnnn_case_1 Actual_SMULL_A1_
cccc0000110shhhhllllmmmm1001nnnn_case_1_instance_; |
| 204 const Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1 Actual_STMDA_
STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_instance_; |
| 201 const Actual_STRB_immediate_cccc010pu1w0nnnnttttiiiiiiiiiiii_case_1 Actual_STR
B_immediate_cccc010pu1w0nnnnttttiiiiiiiiiiii_case_1_instance_; | 205 const Actual_STRB_immediate_cccc010pu1w0nnnnttttiiiiiiiiiiii_case_1 Actual_STR
B_immediate_cccc010pu1w0nnnnttttiiiiiiiiiiii_case_1_instance_; |
| 202 const Actual_STRB_register_cccc011pu1w0nnnnttttiiiiitt0mmmm_case_1 Actual_STRB
_register_cccc011pu1w0nnnnttttiiiiitt0mmmm_case_1_instance_; | 206 const Actual_STRB_register_cccc011pu1w0nnnnttttiiiiitt0mmmm_case_1 Actual_STRB
_register_cccc011pu1w0nnnnttttiiiiitt0mmmm_case_1_instance_; |
| 203 const Actual_STRD_immediate_cccc000pu1w0nnnnttttiiii1111iiii_case_1 Actual_STR
D_immediate_cccc000pu1w0nnnnttttiiii1111iiii_case_1_instance_; | 207 const Actual_STRD_immediate_cccc000pu1w0nnnnttttiiii1111iiii_case_1 Actual_STR
D_immediate_cccc000pu1w0nnnnttttiiii1111iiii_case_1_instance_; |
| 204 const Actual_STRD_register_cccc000pu0w0nnnntttt00001111mmmm_case_1 Actual_STRD
_register_cccc000pu0w0nnnntttt00001111mmmm_case_1_instance_; | 208 const Actual_STRD_register_cccc000pu0w0nnnntttt00001111mmmm_case_1 Actual_STRD
_register_cccc000pu0w0nnnntttt00001111mmmm_case_1_instance_; |
| 205 const Actual_STREXB_cccc00011100nnnndddd11111001tttt_case_1 Actual_STREXB_cccc
00011100nnnndddd11111001tttt_case_1_instance_; | 209 const Actual_STREXB_cccc00011100nnnndddd11111001tttt_case_1 Actual_STREXB_cccc
00011100nnnndddd11111001tttt_case_1_instance_; |
| 206 const Actual_STREXD_cccc00011010nnnndddd11111001tttt_case_1 Actual_STREXD_cccc
00011010nnnndddd11111001tttt_case_1_instance_; | 210 const Actual_STREXD_cccc00011010nnnndddd11111001tttt_case_1 Actual_STREXD_cccc
00011010nnnndddd11111001tttt_case_1_instance_; |
| 207 const Actual_STRH_immediate_cccc000pu1w0nnnnttttiiii1011iiii_case_1 Actual_STR
H_immediate_cccc000pu1w0nnnnttttiiii1011iiii_case_1_instance_; | 211 const Actual_STRH_immediate_cccc000pu1w0nnnnttttiiii1011iiii_case_1 Actual_STR
H_immediate_cccc000pu1w0nnnnttttiiii1011iiii_case_1_instance_; |
| 208 const Actual_STRH_register_cccc000pu0w0nnnntttt00001011mmmm_case_1 Actual_STRH
_register_cccc000pu0w0nnnntttt00001011mmmm_case_1_instance_; | 212 const Actual_STRH_register_cccc000pu0w0nnnntttt00001011mmmm_case_1 Actual_STRH
_register_cccc000pu0w0nnnntttt00001011mmmm_case_1_instance_; |
| 209 const Actual_STR_immediate_cccc010pu0w0nnnnttttiiiiiiiiiiii_case_1 Actual_STR_
immediate_cccc010pu0w0nnnnttttiiiiiiiiiiii_case_1_instance_; | 213 const Actual_STR_immediate_cccc010pu0w0nnnnttttiiiiiiiiiiii_case_1 Actual_STR_
immediate_cccc010pu0w0nnnnttttiiiiiiiiiiii_case_1_instance_; |
| 210 const Actual_STR_register_cccc011pd0w0nnnnttttiiiiitt0mmmm_case_1 Actual_STR_r
egister_cccc011pd0w0nnnnttttiiiiitt0mmmm_case_1_instance_; | 214 const Actual_STR_register_cccc011pd0w0nnnnttttiiiiitt0mmmm_case_1 Actual_STR_r
egister_cccc011pd0w0nnnnttttiiiiitt0mmmm_case_1_instance_; |
| 211 const Actual_SXTAB16_cccc01101000nnnnddddrr000111mmmm_case_1 Actual_SXTAB16_cc
cc01101000nnnnddddrr000111mmmm_case_1_instance_; | 215 const Actual_SXTAB16_cccc01101000nnnnddddrr000111mmmm_case_1 Actual_SXTAB16_cc
cc01101000nnnnddddrr000111mmmm_case_1_instance_; |
| 212 const Actual_TST_immediate_cccc00110001nnnn0000iiiiiiiiiiii_case_1 Actual_TST_
immediate_cccc00110001nnnn0000iiiiiiiiiiii_case_1_instance_; | 216 const Actual_TST_immediate_cccc00110001nnnn0000iiiiiiiiiiii_case_1 Actual_TST_
immediate_cccc00110001nnnn0000iiiiiiiiiiii_case_1_instance_; |
| 213 const Actual_Unnamed_case_1 Actual_Unnamed_case_1_instance_; | 217 const Actual_Unnamed_case_1 Actual_Unnamed_case_1_instance_; |
| 214 const BranchImmediate24 BranchImmediate24_instance_; | |
| 215 const CondVfpOp CondVfpOp_instance_; | 218 const CondVfpOp CondVfpOp_instance_; |
| 216 const DataBarrier DataBarrier_instance_; | 219 const DataBarrier DataBarrier_instance_; |
| 217 const Deprecated Deprecated_instance_; | 220 const Deprecated Deprecated_instance_; |
| 218 const DuplicateToAdvSIMDRegisters DuplicateToAdvSIMDRegisters_instance_; | 221 const DuplicateToAdvSIMDRegisters DuplicateToAdvSIMDRegisters_instance_; |
| 219 const Forbidden Forbidden_instance_; | 222 const Forbidden Forbidden_instance_; |
| 220 const ForbiddenCondDecoder ForbiddenCondDecoder_instance_; | 223 const ForbiddenCondDecoder ForbiddenCondDecoder_instance_; |
| 221 const InstructionBarrier InstructionBarrier_instance_; | 224 const InstructionBarrier InstructionBarrier_instance_; |
| 222 const LoadRegisterList LoadRegisterList_instance_; | |
| 223 const LoadVectorRegister LoadVectorRegister_instance_; | 225 const LoadVectorRegister LoadVectorRegister_instance_; |
| 224 const LoadVectorRegisterList LoadVectorRegisterList_instance_; | 226 const LoadVectorRegisterList LoadVectorRegisterList_instance_; |
| 225 const MoveDoubleVfpRegisterOp MoveDoubleVfpRegisterOp_instance_; | 227 const MoveDoubleVfpRegisterOp MoveDoubleVfpRegisterOp_instance_; |
| 226 const MoveVfpRegisterOp MoveVfpRegisterOp_instance_; | 228 const MoveVfpRegisterOp MoveVfpRegisterOp_instance_; |
| 227 const MoveVfpRegisterOpWithTypeSel MoveVfpRegisterOpWithTypeSel_instance_; | 229 const MoveVfpRegisterOpWithTypeSel MoveVfpRegisterOpWithTypeSel_instance_; |
| 228 const PermanentlyUndefined PermanentlyUndefined_instance_; | 230 const PermanentlyUndefined PermanentlyUndefined_instance_; |
| 229 const PreloadRegisterImm12Op PreloadRegisterImm12Op_instance_; | 231 const PreloadRegisterImm12Op PreloadRegisterImm12Op_instance_; |
| 230 const PreloadRegisterPairOp PreloadRegisterPairOp_instance_; | 232 const PreloadRegisterPairOp PreloadRegisterPairOp_instance_; |
| 231 const StoreRegisterList StoreRegisterList_instance_; | |
| 232 const StoreVectorRegister StoreVectorRegister_instance_; | 233 const StoreVectorRegister StoreVectorRegister_instance_; |
| 233 const StoreVectorRegisterList StoreVectorRegisterList_instance_; | 234 const StoreVectorRegisterList StoreVectorRegisterList_instance_; |
| 234 const Undefined Undefined_instance_; | 235 const Undefined Undefined_instance_; |
| 235 const Unpredictable Unpredictable_instance_; | 236 const Unpredictable Unpredictable_instance_; |
| 236 const VcvtPtAndFixedPoint_FloatingPoint VcvtPtAndFixedPoint_FloatingPoint_inst
ance_; | 237 const VcvtPtAndFixedPoint_FloatingPoint VcvtPtAndFixedPoint_FloatingPoint_inst
ance_; |
| 237 const Vector1RegisterImmediate_BIT Vector1RegisterImmediate_BIT_instance_; | 238 const Vector1RegisterImmediate_BIT Vector1RegisterImmediate_BIT_instance_; |
| 238 const Vector1RegisterImmediate_MOV Vector1RegisterImmediate_MOV_instance_; | 239 const Vector1RegisterImmediate_MOV Vector1RegisterImmediate_MOV_instance_; |
| 239 const Vector1RegisterImmediate_MVN Vector1RegisterImmediate_MVN_instance_; | 240 const Vector1RegisterImmediate_MVN Vector1RegisterImmediate_MVN_instance_; |
| 240 const Vector2RegisterMiscellaneous_CVT_F2I Vector2RegisterMiscellaneous_CVT_F2
I_instance_; | 241 const Vector2RegisterMiscellaneous_CVT_F2I Vector2RegisterMiscellaneous_CVT_F2
I_instance_; |
| 241 const Vector2RegisterMiscellaneous_CVT_H2S Vector2RegisterMiscellaneous_CVT_H2
S_instance_; | 242 const Vector2RegisterMiscellaneous_CVT_H2S Vector2RegisterMiscellaneous_CVT_H2
S_instance_; |
| (...skipping 43 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 285 const VectorLoadStoreSingle3 VectorLoadStoreSingle3_instance_; | 286 const VectorLoadStoreSingle3 VectorLoadStoreSingle3_instance_; |
| 286 const VectorLoadStoreSingle4 VectorLoadStoreSingle4_instance_; | 287 const VectorLoadStoreSingle4 VectorLoadStoreSingle4_instance_; |
| 287 const VectorUnary2RegisterDup VectorUnary2RegisterDup_instance_; | 288 const VectorUnary2RegisterDup VectorUnary2RegisterDup_instance_; |
| 288 const VfpMrsOp VfpMrsOp_instance_; | 289 const VfpMrsOp VfpMrsOp_instance_; |
| 289 const VfpUsesRegOp VfpUsesRegOp_instance_; | 290 const VfpUsesRegOp VfpUsesRegOp_instance_; |
| 290 const NotImplemented not_implemented_; | 291 const NotImplemented not_implemented_; |
| 291 }; | 292 }; |
| 292 | 293 |
| 293 } // namespace nacl_arm_dec | 294 } // namespace nacl_arm_dec |
| 294 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_ | 295 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_ |
| OLD | NEW |