Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_actuals_1.cc

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_actuals.h"
@@ skipping 666 matching lines @@
   // uses: '{inst(3:0)}'
   return RegisterList().
    Add(Register((inst.Bits() & 0x0000000F)));
 }
 
 // Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1
 //
 // Actual:
 //   {defs: {15, 14},
 //    relative: true,
-//    relative_offset: SignExtend(inst(23:0):'00'(1:0), 32),
+//    relative_offset: SignExtend(inst(23:0):'00'(1:0), 32) + 8,
 //    safety: [true => MAY_BE_SAFE],
 //    uses: {15}}
 
 RegisterList Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 defs(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // defs: '{15, 14}'
   return RegisterList().
    Add(Register(15)).
    Add(Register(14));
 }
 
 bool Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 is_relative_branch(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // relative: 'true'
   return true;
 }
 
 int32_t Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 branch_target_offset(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32)"
+  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32) + 8"
   return (((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) & 0x02000000)
        ? ((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) | 0xFC000000)
-       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003)));
+       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) + 8;
 }
 
 SafetyLevel Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // true => MAY_BE_SAFE
   if (true)
     return MAY_BE_SAFE;
 
   return MAY_BE_SAFE;
 }
 
 
 RegisterList Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{15}'
   return RegisterList().
    Add(Register(15));
 }
 
 // Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1
 //
 // Actual:
 //   {defs: {15},
 //    relative: true,
-//    relative_offset: SignExtend(inst(23:0):'00'(1:0), 32),
+//    relative_offset: SignExtend(inst(23:0):'00'(1:0), 32) + 8,
 //    safety: [true => MAY_BE_SAFE],
 //    uses: {15}}
 
 RegisterList Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 defs(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // defs: '{15}'
   return RegisterList().
    Add(Register(15));
 }
 
 bool Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 is_relative_branch(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // relative: 'true'
   return true;
 }
 
 int32_t Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 branch_target_offset(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32)"
+  // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32) + 8"
   return (((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) & 0x02000000)
        ? ((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) | 0xFC000000)
-       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003)));
+       : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) + 8;
 }
 
 SafetyLevel Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // true => MAY_BE_SAFE
   if (true)
     return MAY_BE_SAFE;
 
@@ skipping 328 matching lines @@
 //    defs: Union({inst(19:16)
 //         if inst(21)=1
 //         else 32}, RegisterList(inst(15:0))),
 //    safety: [15  ==
 //            inst(19:16) ||
 //         NumGPRs(RegisterList(inst(15:0)))  <
 //            1 => UNPREDICTABLE,
 //      Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS,
 //      inst(21)=1 &&
 //         Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN],
-//    small_imm_base_wb: true,
+//    small_imm_base_wb: inst(21)=1,
 //    uses: {inst(19:16)}}
 
 Register Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1::
@@ skipping 33 matching lines @@
     return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 
 bool Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{inst(19:16)}'
   return RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
 }
 
@@ skipping 2735 matching lines @@
 //         if inst(21)=1
 //         else 32},
 //    safety: [15  ==
 //            inst(19:16) ||
 //         NumGPRs(RegisterList(inst(15:0)))  <
 //            1 => UNPREDICTABLE,
 //      inst(21)=1 &&
 //         Contains(RegisterList(inst(15:0)), inst(19:16)) &&
 //         SmallestGPR(RegisterList(inst(15:0)))  !=
 //            inst(19:16) => UNKNOWN],
-//    small_imm_base_wb: true,
+//    small_imm_base_wb: inst(21)=1,
 //    uses: Union({inst(19:16)}, RegisterList(inst(15:0)))}
 
 Register Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1::
@@ skipping 32 matching lines @@
     return UNKNOWN;
 
   return MAY_BE_SAFE;
 }
 
 
 bool Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: 'Union({inst(19:16)}, RegisterList(inst(15:0)))'
   return nacl_arm_dec::Union(RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
 }
 
@@ skipping 1166 matching lines @@
 
 
 RegisterList Actual_VABA_1111001u0dssnnnndddd0111nqm1mmmm_case_1::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{}'
   return RegisterList();
 }
 
 }  // namespace nacl_arm_dec