Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode.cc

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h"
 
 namespace nacl_arm_dec {
 
 
 Arm32DecoderState::Arm32DecoderState() : DecoderState()
   , Actual_ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_1_instance_()
   , Actual_ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_1_instance_()
   , Actual_ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_1_instance_()
   , Actual_ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_1_instance_()
   , Actual_ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_1_instance_()
   , Actual_ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_1_instance_()
   , Actual_ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_1_instance_()
   , Actual_BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_1_instance_()
   , Actual_BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_1_instance_()
   , Actual_BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_()
   , Actual_BLX_register_cccc000100101111111111110011mmmm_case_1_instance_()
+  , Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_()
+  , Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_()
   , Actual_Bx_cccc000100101111111111110001mmmm_case_1_instance_()
   , Actual_CLZ_cccc000101101111dddd11110001mmmm_case_1_instance_()
   , Actual_CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_1_instance_()
   , Actual_CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_1_instance_()
   , Actual_CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_1_instance_()
+  , Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_instance_()
   , Actual_LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_1_instance_()
   , Actual_LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_1_instance_()
   , Actual_LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_1_instance_()
   , Actual_LDREXB_cccc00011101nnnntttt111110011111_case_1_instance_()
   , Actual_LDREXD_cccc00011011nnnntttt111110011111_case_1_instance_()
   , Actual_LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_1_instance_()
   , Actual_LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_1_instance_()
   , Actual_LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_1_instance_()
   , Actual_LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_1_instance_()
   , Actual_MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_1_instance_()
   , Actual_MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_1_instance_()
   , Actual_MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_1_instance_()
   , Actual_MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_1_instance_()
   , Actual_MRS_cccc00010r001111dddd000000000000_case_1_instance_()
   , Actual_MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_1_instance_()
   , Actual_MSR_register_cccc00010010mm00111100000000nnnn_case_1_instance_()
   , Actual_MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_1_instance_()
   , Actual_NOP_cccc0011001000001111000000000000_case_1_instance_()
   , Actual_ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_1_instance_()
   , Actual_PKH_cccc01101000nnnnddddiiiiit01mmmm_case_1_instance_()
   , Actual_SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_1_instance_()
   , Actual_SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_1_instance_()
   , Actual_SMULBB_SMULBT_SMULTB_SMULTT_cccc00010110dddd0000mmmm1xx0nnnn_case_1_instance_()
   , Actual_SMULL_A1_cccc0000110shhhhllllmmmm1001nnnn_case_1_instance_()
+  , Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_instance_()
   , Actual_STRD_immediate_cccc000pu1w0nnnnttttiiii1111iiii_case_1_instance_()
   , Actual_STRD_register_cccc000pu0w0nnnntttt00001111mmmm_case_1_instance_()
   , Actual_STREXB_cccc00011100nnnndddd11111001tttt_case_1_instance_()
   , Actual_STREXD_cccc00011010nnnndddd11111001tttt_case_1_instance_()
   , Actual_STRH_immediate_cccc000pu1w0nnnnttttiiii1011iiii_case_1_instance_()
   , Actual_STRH_register_cccc000pu0w0nnnntttt00001011mmmm_case_1_instance_()
   , Actual_TST_immediate_cccc00110001nnnn0000iiiiiiiiiiii_case_1_instance_()
   , Actual_Unnamed_case_1_instance_()
   , Binary2RegisterBitRangeMsbGeLsb_instance_()
   , Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_instance_()
   , Binary3RegisterOpAltA_instance_()
   , Binary3RegisterOpAltANoCondsUpdate_instance_()
   , Binary3RegisterOpAltBNoCondUpdates_instance_()
   , Binary4RegisterDualOp_instance_()
   , Binary4RegisterDualOpNoCondsUpdate_instance_()
   , Binary4RegisterDualResultNoCondsUpdate_instance_()
-  , BranchImmediate24_instance_()
   , CondVfpOp_instance_()
   , DataBarrier_instance_()
   , Deprecated_instance_()
   , DuplicateToAdvSIMDRegisters_instance_()
   , Forbidden_instance_()
   , ForbiddenCondDecoder_instance_()
   , InstructionBarrier_instance_()
   , LdrImmediateOp_instance_()
   , Load2RegisterImm12Op_instance_()
   , Load3RegisterImm5Op_instance_()
-  , LoadRegisterList_instance_()
   , LoadVectorRegister_instance_()
   , LoadVectorRegisterList_instance_()
   , MoveDoubleVfpRegisterOp_instance_()
   , MoveVfpRegisterOp_instance_()
   , MoveVfpRegisterOpWithTypeSel_instance_()
   , PermanentlyUndefined_instance_()
   , PreloadRegisterImm12Op_instance_()
   , PreloadRegisterPairOp_instance_()
   , Store2RegisterImm12Op_instance_()
   , Store3RegisterImm5Op_instance_()
-  , StoreRegisterList_instance_()
   , StoreVectorRegister_instance_()
   , StoreVectorRegisterList_instance_()
   , Unary1RegisterBitRangeMsbGeLsb_instance_()
   , Unary2RegisterImmedShiftedOp_instance_()
   , Unary2RegisterSatImmedShiftedOp_instance_()
   , Undefined_instance_()
   , Unpredictable_instance_()
   , VcvtPtAndFixedPoint_FloatingPoint_instance_()
   , Vector1RegisterImmediate_BIT_instance_()
   , Vector1RegisterImmediate_MOV_instance_()
@@ skipping 383 matching lines @@
 }
 
 // Implementation of table: branch_branch_with_link_and_block_data_transfer.
 // Specified by: See Section A5.5
 const ClassDecoder& Arm32DecoderState::decode_branch_branch_with_link_and_block_data_transfer(
      const Instruction inst) const
 {
   UNREFERENCED_PARAMETER(inst);
   if ((inst.Bits() & 0x02500000)  ==
           0x00000000 /* op(25:20)=0xx0x0 */) {
-    return StoreRegisterList_instance_;
+    return Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_instance_;
   }
 
   if ((inst.Bits() & 0x02500000)  ==
           0x00100000 /* op(25:20)=0xx0x1 */) {
-    return LoadRegisterList_instance_;
+    return Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_instance_;
   }
 
   if ((inst.Bits() & 0x02500000)  ==
           0x00400000 /* op(25:20)=0xx1x0 */ &&
       (inst.Bits() & 0x00200000)  ==
           0x00000000 /* $pattern(31:0)=xxxxxxxxxx0xxxxxxxxxxxxxxxxxxxxx */) {
     return ForbiddenCondDecoder_instance_;
   }
 
   if ((inst.Bits() & 0x02500000)  ==
           0x00500000 /* op(25:20)=0xx1x1 */ &&
       (inst.Bits() & 0x00008000)  ==
           0x00000000 /* R(15)=0 */ &&
       (inst.Bits() & 0x00200000)  ==
           0x00000000 /* $pattern(31:0)=xxxxxxxxxx0xxxxxxxxxxxxxxxxxxxxx */) {
     return ForbiddenCondDecoder_instance_;
   }
 
   if ((inst.Bits() & 0x02500000)  ==
           0x00500000 /* op(25:20)=0xx1x1 */ &&
       (inst.Bits() & 0x00008000)  ==
           0x00008000 /* R(15)=1 */) {
     return ForbiddenCondDecoder_instance_;
   }
 
-  if ((inst.Bits() & 0x02000000)  ==
-          0x02000000 /* op(25:20)=1xxxxx */) {
-    return BranchImmediate24_instance_;
+  if ((inst.Bits() & 0x03000000)  ==
+          0x02000000 /* op(25:20)=10xxxx */) {
+    return Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_;
+  }
+
+  if ((inst.Bits() & 0x03000000)  ==
+          0x03000000 /* op(25:20)=11xxxx */) {
+    return Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1_instance_;
   }
 
   // Catch any attempt to fall though ...
   return not_implemented_;
 }
 
 // Implementation of table: coprocessor_instructions_and_supervisor_call.
 // Specified by: See Section A5.6
 const ClassDecoder& Arm32DecoderState::decode_coprocessor_instructions_and_supervisor_call(
      const Instruction inst) const
@@ skipping 2666 matching lines @@
 
   // Catch any attempt to fall though ...
   return not_implemented_;
 }
 
 const ClassDecoder& Arm32DecoderState::decode(const Instruction inst) const {
   return decode_ARMv7(inst);
 }
 
 }  // namespace nacl_arm_dec