Merge GDB 7.5.1

bfd/doc/reloc.texi

Index: bfd/doc/reloc.texi
diff --git a/bfd/doc/reloc.texi b/bfd/doc/reloc.texi
index d1fb2c8b3e446c82e2eb57a4964b5e7dcaca9aad..b1f9bb91b1219b73abf1b3135352ceff85e1af3f 100644
--- a/bfd/doc/reloc.texi
+++ b/bfd/doc/reloc.texi
@@ -662,6 +662,10 @@ I think these are specific to SPARC a.out (e.g., Sun 4).
 @deffnx {} BFD_RELOC_SPARC_M44
 @deffnx {} BFD_RELOC_SPARC_L44
 @deffnx {} BFD_RELOC_SPARC_REGISTER
+@deffnx {} BFD_RELOC_SPARC_H34
+@deffnx {} BFD_RELOC_SPARC_SIZE32
+@deffnx {} BFD_RELOC_SPARC_SIZE64
+@deffnx {} BFD_RELOC_SPARC_WDISP10
 SPARC64 relocations
 @end deffn
 @deffn {} BFD_RELOC_SPARC_REV32
@@ -858,6 +862,15 @@ to compensate for the borrow when the low bits are added.
 @deffn {} BFD_RELOC_MIPS16_LO16
 MIPS16 low 16 bits.
 @end deffn
+@deffn {} BFD_RELOC_MIPS16_TLS_GD
+@deffnx {} BFD_RELOC_MIPS16_TLS_LDM
+@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16
+@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16
+@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL
+@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16
+@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16
+MIPS16 TLS relocations
+@end deffn
 @deffn {} BFD_RELOC_MIPS_LITERAL
 @deffnx {} BFD_RELOC_MICROMIPS_LITERAL
 Relocation against a MIPS literal section.
@@ -1015,6 +1028,25 @@ The addend of this reloc is an alignment power that must
 be honoured at the offset's location, regardless of linker
 relaxation.
 @end deffn
+@deffn {} BFD_RELOC_MN10300_TLS_GD
+@deffnx {} BFD_RELOC_MN10300_TLS_LD
+@deffnx {} BFD_RELOC_MN10300_TLS_LDO
+@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE
+@deffnx {} BFD_RELOC_MN10300_TLS_IE
+@deffnx {} BFD_RELOC_MN10300_TLS_LE
+@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD
+@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF
+@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF
+Various TLS-related relocations.
+@end deffn
+@deffn {} BFD_RELOC_MN10300_32_PCREL
+This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
+instruction.
+@end deffn
+@deffn {} BFD_RELOC_MN10300_16_PCREL
+This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
+instruction.
+@end deffn
 @deffn {} BFD_RELOC_386_GOT32
 @deffnx {} BFD_RELOC_386_PLT32
 @deffnx {} BFD_RELOC_386_COPY
@@ -1126,6 +1158,23 @@ Picojava relocs.  Not all of these appear in object files.
 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA
+@deffnx {} BFD_RELOC_PPC_VLE_REL8
+@deffnx {} BFD_RELOC_PPC_VLE_REL15
+@deffnx {} BFD_RELOC_PPC_VLE_REL24
+@deffnx {} BFD_RELOC_PPC_VLE_LO16A
+@deffnx {} BFD_RELOC_PPC_VLE_LO16D
+@deffnx {} BFD_RELOC_PPC_VLE_HI16A
+@deffnx {} BFD_RELOC_PPC_VLE_HI16D
+@deffnx {} BFD_RELOC_PPC_VLE_HA16A
+@deffnx {} BFD_RELOC_PPC_VLE_HA16D
+@deffnx {} BFD_RELOC_PPC_VLE_SDA21
+@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D
 @deffnx {} BFD_RELOC_PPC64_HIGHER
 @deffnx {} BFD_RELOC_PPC64_HIGHER_S
 @deffnx {} BFD_RELOC_PPC64_HIGHEST
@@ -1849,14 +1898,6 @@ start code.
 @deffn {} BFD_RELOC_V850_DATA
 start data in text.
 @end deffn
-@deffn {} BFD_RELOC_MN10300_32_PCREL
-This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
-instruction.
-@end deffn
-@deffn {} BFD_RELOC_MN10300_16_PCREL
-This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
-instruction.
-@end deffn
 @deffn {} BFD_RELOC_TIC30_LDP
 This is a 8bit DP reloc for the tms320c30, where the most
 significant 8 bits of a 24 bit word are placed into the least
@@ -2127,6 +2168,18 @@ instructions
 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
 instructions
 @end deffn
+@deffn {} BFD_RELOC_AVR_8_LO
+This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
+in .byte lo8(symbol)
+@end deffn
+@deffn {} BFD_RELOC_AVR_8_HI
+This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
+in .byte hi8(symbol)
+@end deffn
+@deffn {} BFD_RELOC_AVR_8_HLO
+This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
+in .byte hlo8(symbol)
+@end deffn
 @deffn {} BFD_RELOC_RL78_NEG8
 @deffnx {} BFD_RELOC_RL78_NEG16
 @deffnx {} BFD_RELOC_RL78_NEG24
@@ -2296,6 +2349,9 @@ s390 tls relocations.
 @deffnx {} BFD_RELOC_390_TLS_GOTIE20
 Long displacement extension.
 @end deffn
+@deffn {} BFD_RELOC_390_IRELATIVE
+STT_GNU_IFUNC relocation.
+@end deffn
 @deffn {} BFD_RELOC_SCORE_GPREL15
 Score relocations
 Low 16 bit for load/store
@@ -2510,6 +2566,83 @@ to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
 Motorola 68HC12 reloc.
 This is the 5 bits of a value.
 @end deffn
+@deffn {} BFD_RELOC_XGATE_RL_JUMP
+Freescale XGATE reloc.
+This reloc marks the beginning of a bra/jal instruction.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_RL_GROUP
+Freescale XGATE reloc.
+This reloc marks a group of several instructions that gcc generates
+and for which the linker relaxation pass can modify and/or remove
+some of them.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_LO16
+Freescale XGATE reloc.
+This is the 16-bit lower part of an address.  It is used for the '16-bit'
+instructions.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_GPAGE
+Freescale XGATE reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_24
+Freescale XGATE reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_PCREL_9
+Freescale XGATE reloc.
+This is a 9-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_PCREL_10
+Freescale XGATE reloc.
+This is a 10-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM8_LO
+Freescale XGATE reloc.
+This is the 16-bit lower part of an address.  It is used for the '16-bit'
+instructions.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM8_HI
+Freescale XGATE reloc.
+This is the 16-bit higher part of an address.  It is used for the '16-bit'
+instructions.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM3
+Freescale XGATE reloc.
+This is a 3-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM4
+Freescale XGATE reloc.
+This is a 4-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM5
+Freescale XGATE reloc.
+This is a 5-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_9B
+Motorola 68HC12 reloc.
+This is the 9 bits of a value.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_16B
+Motorola 68HC12 reloc.
+This is the 16 bits of a value.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_9_PCREL
+Motorola 68HC12/XGATE reloc.
+This is a PCREL9 branch.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_10_PCREL
+Motorola 68HC12/XGATE reloc.
+This is a PCREL10 branch.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_LO8XG
+Motorola 68HC12/XGATE reloc.
+This is the 8 bit low part of an absolute address and immediately precedes
+a matching HI8XG part.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_HI8XG
+Motorola 68HC12/XGATE reloc.
+This is the 8 bit high part of an absolute address and immediately follows
+a matching LO8XG part.
+@end deffn
 @deffn {} BFD_RELOC_16C_NUM08
 @deffnx {} BFD_RELOC_16C_NUM08_C
 @deffnx {} BFD_RELOC_16C_NUM16
@@ -2875,6 +3008,9 @@ Lattice Mico32 relocations.
 Difference between two section addreses.  Must be followed by a
 BFD_RELOC_MACH_O_PAIR.
 @end deffn
+@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF
+Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
+@end deffn
 @deffn {} BFD_RELOC_MACH_O_PAIR
 Pair of relocation.  Contains the first symbol.
 @end deffn
@@ -3004,6 +3140,12 @@ the dynamic object into the runtime process image.
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1
+@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
@@ -3023,6 +3165,14 @@ the dynamic object into the runtime process image.
 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32
 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32
 @deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
 Tilera TILEPro Relocations.
 @end deffn
 @deffn {} BFD_RELOC_TILEGX_HW0
@@ -3082,52 +3232,44 @@ Tilera TILEPro Relocations.
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64
 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32
 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32
+@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
 Tilera TILE-Gx Relocations.
 @end deffn
 @deffn {} BFD_RELOC_EPIPHANY_SIMM8
@@ -3219,12 +3361,13 @@ don't do section gc -- i.e., does nothing.
 @subsubsection @code{bfd_generic_lookup_section_flags}
 @strong{Synopsis}
 @example
-void bfd_generic_lookup_section_flags
-   (struct bfd_link_info *, struct flag_info *);
+bfd_boolean bfd_generic_lookup_section_flags
+   (struct bfd_link_info *, struct flag_info *, asection *);
 @end example
 @strong{Description}@*
 Provides default handling for section flags lookup
 -- i.e., does nothing.
+Returns FALSE if the section should be omitted, otherwise TRUE.
 
 @findex bfd_generic_merge_sections
 @subsubsection @code{bfd_generic_merge_sections}