OLD | NEW |
1 @section Relocations | 1 @section Relocations |
2 BFD maintains relocations in much the same way it maintains | 2 BFD maintains relocations in much the same way it maintains |
3 symbols: they are left alone until required, then read in | 3 symbols: they are left alone until required, then read in |
4 en-masse and translated into an internal form. A common | 4 en-masse and translated into an internal form. A common |
5 routine @code{bfd_perform_relocation} acts upon the | 5 routine @code{bfd_perform_relocation} acts upon the |
6 canonical form to do the fixup. | 6 canonical form to do the fixup. |
7 | 7 |
8 Relocations are maintained on a per section basis, | 8 Relocations are maintained on a per section basis, |
9 while symbols are maintained on a per BFD basis. | 9 while symbols are maintained on a per BFD basis. |
10 | 10 |
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655 @deffnx {} BFD_RELOC_SPARC_5 | 655 @deffnx {} BFD_RELOC_SPARC_5 |
656 @deffnx {} BFD_RELOC_SPARC_DISP64 | 656 @deffnx {} BFD_RELOC_SPARC_DISP64 |
657 @deffnx {} BFD_RELOC_SPARC_PLT32 | 657 @deffnx {} BFD_RELOC_SPARC_PLT32 |
658 @deffnx {} BFD_RELOC_SPARC_PLT64 | 658 @deffnx {} BFD_RELOC_SPARC_PLT64 |
659 @deffnx {} BFD_RELOC_SPARC_HIX22 | 659 @deffnx {} BFD_RELOC_SPARC_HIX22 |
660 @deffnx {} BFD_RELOC_SPARC_LOX10 | 660 @deffnx {} BFD_RELOC_SPARC_LOX10 |
661 @deffnx {} BFD_RELOC_SPARC_H44 | 661 @deffnx {} BFD_RELOC_SPARC_H44 |
662 @deffnx {} BFD_RELOC_SPARC_M44 | 662 @deffnx {} BFD_RELOC_SPARC_M44 |
663 @deffnx {} BFD_RELOC_SPARC_L44 | 663 @deffnx {} BFD_RELOC_SPARC_L44 |
664 @deffnx {} BFD_RELOC_SPARC_REGISTER | 664 @deffnx {} BFD_RELOC_SPARC_REGISTER |
| 665 @deffnx {} BFD_RELOC_SPARC_H34 |
| 666 @deffnx {} BFD_RELOC_SPARC_SIZE32 |
| 667 @deffnx {} BFD_RELOC_SPARC_SIZE64 |
| 668 @deffnx {} BFD_RELOC_SPARC_WDISP10 |
665 SPARC64 relocations | 669 SPARC64 relocations |
666 @end deffn | 670 @end deffn |
667 @deffn {} BFD_RELOC_SPARC_REV32 | 671 @deffn {} BFD_RELOC_SPARC_REV32 |
668 SPARC little endian relocation | 672 SPARC little endian relocation |
669 @end deffn | 673 @end deffn |
670 @deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 | 674 @deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 |
671 @deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 | 675 @deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 |
672 @deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD | 676 @deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD |
673 @deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL | 677 @deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL |
674 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 | 678 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 |
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851 @end deffn | 855 @end deffn |
852 @deffn {} BFD_RELOC_MIPS16_HI16_S | 856 @deffn {} BFD_RELOC_MIPS16_HI16_S |
853 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign | 857 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign |
854 extended and added to form the final result. If the low 16 | 858 extended and added to form the final result. If the low 16 |
855 bits form a negative number, we need to add one to the high value | 859 bits form a negative number, we need to add one to the high value |
856 to compensate for the borrow when the low bits are added. | 860 to compensate for the borrow when the low bits are added. |
857 @end deffn | 861 @end deffn |
858 @deffn {} BFD_RELOC_MIPS16_LO16 | 862 @deffn {} BFD_RELOC_MIPS16_LO16 |
859 MIPS16 low 16 bits. | 863 MIPS16 low 16 bits. |
860 @end deffn | 864 @end deffn |
| 865 @deffn {} BFD_RELOC_MIPS16_TLS_GD |
| 866 @deffnx {} BFD_RELOC_MIPS16_TLS_LDM |
| 867 @deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 |
| 868 @deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 |
| 869 @deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL |
| 870 @deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 |
| 871 @deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 |
| 872 MIPS16 TLS relocations |
| 873 @end deffn |
861 @deffn {} BFD_RELOC_MIPS_LITERAL | 874 @deffn {} BFD_RELOC_MIPS_LITERAL |
862 @deffnx {} BFD_RELOC_MICROMIPS_LITERAL | 875 @deffnx {} BFD_RELOC_MICROMIPS_LITERAL |
863 Relocation against a MIPS literal section. | 876 Relocation against a MIPS literal section. |
864 @end deffn | 877 @end deffn |
865 @deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 | 878 @deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 |
866 @deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 | 879 @deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 |
867 @deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 | 880 @deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 |
868 microMIPS PC-relative relocations. | 881 microMIPS PC-relative relocations. |
869 @end deffn | 882 @end deffn |
870 @deffn {} BFD_RELOC_MICROMIPS_GPREL16 | 883 @deffn {} BFD_RELOC_MICROMIPS_GPREL16 |
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1008 @deffn {} BFD_RELOC_MN10300_SYM_DIFF | 1021 @deffn {} BFD_RELOC_MN10300_SYM_DIFF |
1009 Together with another reloc targeted at the same location, | 1022 Together with another reloc targeted at the same location, |
1010 allows for a value that is the difference of two symbols | 1023 allows for a value that is the difference of two symbols |
1011 in the same section. | 1024 in the same section. |
1012 @end deffn | 1025 @end deffn |
1013 @deffn {} BFD_RELOC_MN10300_ALIGN | 1026 @deffn {} BFD_RELOC_MN10300_ALIGN |
1014 The addend of this reloc is an alignment power that must | 1027 The addend of this reloc is an alignment power that must |
1015 be honoured at the offset's location, regardless of linker | 1028 be honoured at the offset's location, regardless of linker |
1016 relaxation. | 1029 relaxation. |
1017 @end deffn | 1030 @end deffn |
| 1031 @deffn {} BFD_RELOC_MN10300_TLS_GD |
| 1032 @deffnx {} BFD_RELOC_MN10300_TLS_LD |
| 1033 @deffnx {} BFD_RELOC_MN10300_TLS_LDO |
| 1034 @deffnx {} BFD_RELOC_MN10300_TLS_GOTIE |
| 1035 @deffnx {} BFD_RELOC_MN10300_TLS_IE |
| 1036 @deffnx {} BFD_RELOC_MN10300_TLS_LE |
| 1037 @deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD |
| 1038 @deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF |
| 1039 @deffnx {} BFD_RELOC_MN10300_TLS_TPOFF |
| 1040 Various TLS-related relocations. |
| 1041 @end deffn |
| 1042 @deffn {} BFD_RELOC_MN10300_32_PCREL |
| 1043 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the |
| 1044 instruction. |
| 1045 @end deffn |
| 1046 @deffn {} BFD_RELOC_MN10300_16_PCREL |
| 1047 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the |
| 1048 instruction. |
| 1049 @end deffn |
1018 @deffn {} BFD_RELOC_386_GOT32 | 1050 @deffn {} BFD_RELOC_386_GOT32 |
1019 @deffnx {} BFD_RELOC_386_PLT32 | 1051 @deffnx {} BFD_RELOC_386_PLT32 |
1020 @deffnx {} BFD_RELOC_386_COPY | 1052 @deffnx {} BFD_RELOC_386_COPY |
1021 @deffnx {} BFD_RELOC_386_GLOB_DAT | 1053 @deffnx {} BFD_RELOC_386_GLOB_DAT |
1022 @deffnx {} BFD_RELOC_386_JUMP_SLOT | 1054 @deffnx {} BFD_RELOC_386_JUMP_SLOT |
1023 @deffnx {} BFD_RELOC_386_RELATIVE | 1055 @deffnx {} BFD_RELOC_386_RELATIVE |
1024 @deffnx {} BFD_RELOC_386_GOTOFF | 1056 @deffnx {} BFD_RELOC_386_GOTOFF |
1025 @deffnx {} BFD_RELOC_386_GOTPC | 1057 @deffnx {} BFD_RELOC_386_GOTPC |
1026 @deffnx {} BFD_RELOC_386_TLS_TPOFF | 1058 @deffnx {} BFD_RELOC_386_TLS_TPOFF |
1027 @deffnx {} BFD_RELOC_386_TLS_IE | 1059 @deffnx {} BFD_RELOC_386_TLS_IE |
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1119 @deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 | 1151 @deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 |
1120 @deffnx {} BFD_RELOC_PPC_EMB_SDA2REL | 1152 @deffnx {} BFD_RELOC_PPC_EMB_SDA2REL |
1121 @deffnx {} BFD_RELOC_PPC_EMB_SDA21 | 1153 @deffnx {} BFD_RELOC_PPC_EMB_SDA21 |
1122 @deffnx {} BFD_RELOC_PPC_EMB_MRKREF | 1154 @deffnx {} BFD_RELOC_PPC_EMB_MRKREF |
1123 @deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 | 1155 @deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 |
1124 @deffnx {} BFD_RELOC_PPC_EMB_RELST_LO | 1156 @deffnx {} BFD_RELOC_PPC_EMB_RELST_LO |
1125 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HI | 1157 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HI |
1126 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA | 1158 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA |
1127 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD | 1159 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD |
1128 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA | 1160 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA |
| 1161 @deffnx {} BFD_RELOC_PPC_VLE_REL8 |
| 1162 @deffnx {} BFD_RELOC_PPC_VLE_REL15 |
| 1163 @deffnx {} BFD_RELOC_PPC_VLE_REL24 |
| 1164 @deffnx {} BFD_RELOC_PPC_VLE_LO16A |
| 1165 @deffnx {} BFD_RELOC_PPC_VLE_LO16D |
| 1166 @deffnx {} BFD_RELOC_PPC_VLE_HI16A |
| 1167 @deffnx {} BFD_RELOC_PPC_VLE_HI16D |
| 1168 @deffnx {} BFD_RELOC_PPC_VLE_HA16A |
| 1169 @deffnx {} BFD_RELOC_PPC_VLE_HA16D |
| 1170 @deffnx {} BFD_RELOC_PPC_VLE_SDA21 |
| 1171 @deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO |
| 1172 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A |
| 1173 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D |
| 1174 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A |
| 1175 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D |
| 1176 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A |
| 1177 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D |
1129 @deffnx {} BFD_RELOC_PPC64_HIGHER | 1178 @deffnx {} BFD_RELOC_PPC64_HIGHER |
1130 @deffnx {} BFD_RELOC_PPC64_HIGHER_S | 1179 @deffnx {} BFD_RELOC_PPC64_HIGHER_S |
1131 @deffnx {} BFD_RELOC_PPC64_HIGHEST | 1180 @deffnx {} BFD_RELOC_PPC64_HIGHEST |
1132 @deffnx {} BFD_RELOC_PPC64_HIGHEST_S | 1181 @deffnx {} BFD_RELOC_PPC64_HIGHEST_S |
1133 @deffnx {} BFD_RELOC_PPC64_TOC16_LO | 1182 @deffnx {} BFD_RELOC_PPC64_TOC16_LO |
1134 @deffnx {} BFD_RELOC_PPC64_TOC16_HI | 1183 @deffnx {} BFD_RELOC_PPC64_TOC16_HI |
1135 @deffnx {} BFD_RELOC_PPC64_TOC16_HA | 1184 @deffnx {} BFD_RELOC_PPC64_TOC16_HA |
1136 @deffnx {} BFD_RELOC_PPC64_TOC | 1185 @deffnx {} BFD_RELOC_PPC64_TOC |
1137 @deffnx {} BFD_RELOC_PPC64_PLTGOT16 | 1186 @deffnx {} BFD_RELOC_PPC64_PLTGOT16 |
1138 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO | 1187 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO |
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1842 @end deffn | 1891 @end deffn |
1843 @deffn {} BFD_RELOC_V850_32_GOTOFF | 1892 @deffn {} BFD_RELOC_V850_32_GOTOFF |
1844 DSO relocations. | 1893 DSO relocations. |
1845 @end deffn | 1894 @end deffn |
1846 @deffn {} BFD_RELOC_V850_CODE | 1895 @deffn {} BFD_RELOC_V850_CODE |
1847 start code. | 1896 start code. |
1848 @end deffn | 1897 @end deffn |
1849 @deffn {} BFD_RELOC_V850_DATA | 1898 @deffn {} BFD_RELOC_V850_DATA |
1850 start data in text. | 1899 start data in text. |
1851 @end deffn | 1900 @end deffn |
1852 @deffn {} BFD_RELOC_MN10300_32_PCREL | |
1853 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the | |
1854 instruction. | |
1855 @end deffn | |
1856 @deffn {} BFD_RELOC_MN10300_16_PCREL | |
1857 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the | |
1858 instruction. | |
1859 @end deffn | |
1860 @deffn {} BFD_RELOC_TIC30_LDP | 1901 @deffn {} BFD_RELOC_TIC30_LDP |
1861 This is a 8bit DP reloc for the tms320c30, where the most | 1902 This is a 8bit DP reloc for the tms320c30, where the most |
1862 significant 8 bits of a 24 bit word are placed into the least | 1903 significant 8 bits of a 24 bit word are placed into the least |
1863 significant 8 bits of the opcode. | 1904 significant 8 bits of the opcode. |
1864 @end deffn | 1905 @end deffn |
1865 @deffn {} BFD_RELOC_TIC54X_PARTLS7 | 1906 @deffn {} BFD_RELOC_TIC54X_PARTLS7 |
1866 This is a 7bit reloc for the tms320c54x, where the least | 1907 This is a 7bit reloc for the tms320c54x, where the least |
1867 significant 7 bits of a 16 bit word are placed into the least | 1908 significant 7 bits of a 16 bit word are placed into the least |
1868 significant 7 bits of the opcode. | 1909 significant 7 bits of the opcode. |
1869 @end deffn | 1910 @end deffn |
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2120 for absolute addressing with ldi with overflow check to linktime | 2161 for absolute addressing with ldi with overflow check to linktime |
2121 @end deffn | 2162 @end deffn |
2122 @deffn {} BFD_RELOC_AVR_6 | 2163 @deffn {} BFD_RELOC_AVR_6 |
2123 This is a 6 bit reloc for the AVR that stores offset for ldd/std | 2164 This is a 6 bit reloc for the AVR that stores offset for ldd/std |
2124 instructions | 2165 instructions |
2125 @end deffn | 2166 @end deffn |
2126 @deffn {} BFD_RELOC_AVR_6_ADIW | 2167 @deffn {} BFD_RELOC_AVR_6_ADIW |
2127 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw | 2168 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw |
2128 instructions | 2169 instructions |
2129 @end deffn | 2170 @end deffn |
| 2171 @deffn {} BFD_RELOC_AVR_8_LO |
| 2172 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol |
| 2173 in .byte lo8(symbol) |
| 2174 @end deffn |
| 2175 @deffn {} BFD_RELOC_AVR_8_HI |
| 2176 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol |
| 2177 in .byte hi8(symbol) |
| 2178 @end deffn |
| 2179 @deffn {} BFD_RELOC_AVR_8_HLO |
| 2180 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol |
| 2181 in .byte hlo8(symbol) |
| 2182 @end deffn |
2130 @deffn {} BFD_RELOC_RL78_NEG8 | 2183 @deffn {} BFD_RELOC_RL78_NEG8 |
2131 @deffnx {} BFD_RELOC_RL78_NEG16 | 2184 @deffnx {} BFD_RELOC_RL78_NEG16 |
2132 @deffnx {} BFD_RELOC_RL78_NEG24 | 2185 @deffnx {} BFD_RELOC_RL78_NEG24 |
2133 @deffnx {} BFD_RELOC_RL78_NEG32 | 2186 @deffnx {} BFD_RELOC_RL78_NEG32 |
2134 @deffnx {} BFD_RELOC_RL78_16_OP | 2187 @deffnx {} BFD_RELOC_RL78_16_OP |
2135 @deffnx {} BFD_RELOC_RL78_24_OP | 2188 @deffnx {} BFD_RELOC_RL78_24_OP |
2136 @deffnx {} BFD_RELOC_RL78_32_OP | 2189 @deffnx {} BFD_RELOC_RL78_32_OP |
2137 @deffnx {} BFD_RELOC_RL78_8U | 2190 @deffnx {} BFD_RELOC_RL78_8U |
2138 @deffnx {} BFD_RELOC_RL78_16U | 2191 @deffnx {} BFD_RELOC_RL78_16U |
2139 @deffnx {} BFD_RELOC_RL78_24U | 2192 @deffnx {} BFD_RELOC_RL78_24U |
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2289 @deffnx {} BFD_RELOC_390_TLS_DTPOFF | 2342 @deffnx {} BFD_RELOC_390_TLS_DTPOFF |
2290 @deffnx {} BFD_RELOC_390_TLS_TPOFF | 2343 @deffnx {} BFD_RELOC_390_TLS_TPOFF |
2291 s390 tls relocations. | 2344 s390 tls relocations. |
2292 @end deffn | 2345 @end deffn |
2293 @deffn {} BFD_RELOC_390_20 | 2346 @deffn {} BFD_RELOC_390_20 |
2294 @deffnx {} BFD_RELOC_390_GOT20 | 2347 @deffnx {} BFD_RELOC_390_GOT20 |
2295 @deffnx {} BFD_RELOC_390_GOTPLT20 | 2348 @deffnx {} BFD_RELOC_390_GOTPLT20 |
2296 @deffnx {} BFD_RELOC_390_TLS_GOTIE20 | 2349 @deffnx {} BFD_RELOC_390_TLS_GOTIE20 |
2297 Long displacement extension. | 2350 Long displacement extension. |
2298 @end deffn | 2351 @end deffn |
| 2352 @deffn {} BFD_RELOC_390_IRELATIVE |
| 2353 STT_GNU_IFUNC relocation. |
| 2354 @end deffn |
2299 @deffn {} BFD_RELOC_SCORE_GPREL15 | 2355 @deffn {} BFD_RELOC_SCORE_GPREL15 |
2300 Score relocations | 2356 Score relocations |
2301 Low 16 bit for load/store | 2357 Low 16 bit for load/store |
2302 @end deffn | 2358 @end deffn |
2303 @deffn {} BFD_RELOC_SCORE_DUMMY2 | 2359 @deffn {} BFD_RELOC_SCORE_DUMMY2 |
2304 @deffnx {} BFD_RELOC_SCORE_JMP | 2360 @deffnx {} BFD_RELOC_SCORE_JMP |
2305 This is a 24-bit reloc with the right 1 bit assumed to be 0 | 2361 This is a 24-bit reloc with the right 1 bit assumed to be 0 |
2306 @end deffn | 2362 @end deffn |
2307 @deffn {} BFD_RELOC_SCORE_BRANCH | 2363 @deffn {} BFD_RELOC_SCORE_BRANCH |
2308 This is a 19-bit reloc with the right 1 bit assumed to be 0 | 2364 This is a 19-bit reloc with the right 1 bit assumed to be 0 |
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2503 @deffn {} BFD_RELOC_M68HC11_24 | 2559 @deffn {} BFD_RELOC_M68HC11_24 |
2504 Motorola 68HC11 reloc. | 2560 Motorola 68HC11 reloc. |
2505 This is a 24-bit reloc that represents the address with a 16-bit | 2561 This is a 24-bit reloc that represents the address with a 16-bit |
2506 value and a 8-bit page number. The symbol address is transformed | 2562 value and a 8-bit page number. The symbol address is transformed |
2507 to follow the 16K memory bank of 68HC12 (seen as mapped in the window). | 2563 to follow the 16K memory bank of 68HC12 (seen as mapped in the window). |
2508 @end deffn | 2564 @end deffn |
2509 @deffn {} BFD_RELOC_M68HC12_5B | 2565 @deffn {} BFD_RELOC_M68HC12_5B |
2510 Motorola 68HC12 reloc. | 2566 Motorola 68HC12 reloc. |
2511 This is the 5 bits of a value. | 2567 This is the 5 bits of a value. |
2512 @end deffn | 2568 @end deffn |
| 2569 @deffn {} BFD_RELOC_XGATE_RL_JUMP |
| 2570 Freescale XGATE reloc. |
| 2571 This reloc marks the beginning of a bra/jal instruction. |
| 2572 @end deffn |
| 2573 @deffn {} BFD_RELOC_XGATE_RL_GROUP |
| 2574 Freescale XGATE reloc. |
| 2575 This reloc marks a group of several instructions that gcc generates |
| 2576 and for which the linker relaxation pass can modify and/or remove |
| 2577 some of them. |
| 2578 @end deffn |
| 2579 @deffn {} BFD_RELOC_XGATE_LO16 |
| 2580 Freescale XGATE reloc. |
| 2581 This is the 16-bit lower part of an address. It is used for the '16-bit' |
| 2582 instructions. |
| 2583 @end deffn |
| 2584 @deffn {} BFD_RELOC_XGATE_GPAGE |
| 2585 Freescale XGATE reloc. |
| 2586 @end deffn |
| 2587 @deffn {} BFD_RELOC_XGATE_24 |
| 2588 Freescale XGATE reloc. |
| 2589 @end deffn |
| 2590 @deffn {} BFD_RELOC_XGATE_PCREL_9 |
| 2591 Freescale XGATE reloc. |
| 2592 This is a 9-bit pc-relative reloc. |
| 2593 @end deffn |
| 2594 @deffn {} BFD_RELOC_XGATE_PCREL_10 |
| 2595 Freescale XGATE reloc. |
| 2596 This is a 10-bit pc-relative reloc. |
| 2597 @end deffn |
| 2598 @deffn {} BFD_RELOC_XGATE_IMM8_LO |
| 2599 Freescale XGATE reloc. |
| 2600 This is the 16-bit lower part of an address. It is used for the '16-bit' |
| 2601 instructions. |
| 2602 @end deffn |
| 2603 @deffn {} BFD_RELOC_XGATE_IMM8_HI |
| 2604 Freescale XGATE reloc. |
| 2605 This is the 16-bit higher part of an address. It is used for the '16-bit' |
| 2606 instructions. |
| 2607 @end deffn |
| 2608 @deffn {} BFD_RELOC_XGATE_IMM3 |
| 2609 Freescale XGATE reloc. |
| 2610 This is a 3-bit pc-relative reloc. |
| 2611 @end deffn |
| 2612 @deffn {} BFD_RELOC_XGATE_IMM4 |
| 2613 Freescale XGATE reloc. |
| 2614 This is a 4-bit pc-relative reloc. |
| 2615 @end deffn |
| 2616 @deffn {} BFD_RELOC_XGATE_IMM5 |
| 2617 Freescale XGATE reloc. |
| 2618 This is a 5-bit pc-relative reloc. |
| 2619 @end deffn |
| 2620 @deffn {} BFD_RELOC_M68HC12_9B |
| 2621 Motorola 68HC12 reloc. |
| 2622 This is the 9 bits of a value. |
| 2623 @end deffn |
| 2624 @deffn {} BFD_RELOC_M68HC12_16B |
| 2625 Motorola 68HC12 reloc. |
| 2626 This is the 16 bits of a value. |
| 2627 @end deffn |
| 2628 @deffn {} BFD_RELOC_M68HC12_9_PCREL |
| 2629 Motorola 68HC12/XGATE reloc. |
| 2630 This is a PCREL9 branch. |
| 2631 @end deffn |
| 2632 @deffn {} BFD_RELOC_M68HC12_10_PCREL |
| 2633 Motorola 68HC12/XGATE reloc. |
| 2634 This is a PCREL10 branch. |
| 2635 @end deffn |
| 2636 @deffn {} BFD_RELOC_M68HC12_LO8XG |
| 2637 Motorola 68HC12/XGATE reloc. |
| 2638 This is the 8 bit low part of an absolute address and immediately precedes |
| 2639 a matching HI8XG part. |
| 2640 @end deffn |
| 2641 @deffn {} BFD_RELOC_M68HC12_HI8XG |
| 2642 Motorola 68HC12/XGATE reloc. |
| 2643 This is the 8 bit high part of an absolute address and immediately follows |
| 2644 a matching LO8XG part. |
| 2645 @end deffn |
2513 @deffn {} BFD_RELOC_16C_NUM08 | 2646 @deffn {} BFD_RELOC_16C_NUM08 |
2514 @deffnx {} BFD_RELOC_16C_NUM08_C | 2647 @deffnx {} BFD_RELOC_16C_NUM08_C |
2515 @deffnx {} BFD_RELOC_16C_NUM16 | 2648 @deffnx {} BFD_RELOC_16C_NUM16 |
2516 @deffnx {} BFD_RELOC_16C_NUM16_C | 2649 @deffnx {} BFD_RELOC_16C_NUM16_C |
2517 @deffnx {} BFD_RELOC_16C_NUM32 | 2650 @deffnx {} BFD_RELOC_16C_NUM32 |
2518 @deffnx {} BFD_RELOC_16C_NUM32_C | 2651 @deffnx {} BFD_RELOC_16C_NUM32_C |
2519 @deffnx {} BFD_RELOC_16C_DISP04 | 2652 @deffnx {} BFD_RELOC_16C_DISP04 |
2520 @deffnx {} BFD_RELOC_16C_DISP04_C | 2653 @deffnx {} BFD_RELOC_16C_DISP04_C |
2521 @deffnx {} BFD_RELOC_16C_DISP08 | 2654 @deffnx {} BFD_RELOC_16C_DISP08 |
2522 @deffnx {} BFD_RELOC_16C_DISP08_C | 2655 @deffnx {} BFD_RELOC_16C_DISP08_C |
(...skipping 345 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2868 @deffnx {} BFD_RELOC_LM32_COPY | 3001 @deffnx {} BFD_RELOC_LM32_COPY |
2869 @deffnx {} BFD_RELOC_LM32_GLOB_DAT | 3002 @deffnx {} BFD_RELOC_LM32_GLOB_DAT |
2870 @deffnx {} BFD_RELOC_LM32_JMP_SLOT | 3003 @deffnx {} BFD_RELOC_LM32_JMP_SLOT |
2871 @deffnx {} BFD_RELOC_LM32_RELATIVE | 3004 @deffnx {} BFD_RELOC_LM32_RELATIVE |
2872 Lattice Mico32 relocations. | 3005 Lattice Mico32 relocations. |
2873 @end deffn | 3006 @end deffn |
2874 @deffn {} BFD_RELOC_MACH_O_SECTDIFF | 3007 @deffn {} BFD_RELOC_MACH_O_SECTDIFF |
2875 Difference between two section addreses. Must be followed by a | 3008 Difference between two section addreses. Must be followed by a |
2876 BFD_RELOC_MACH_O_PAIR. | 3009 BFD_RELOC_MACH_O_PAIR. |
2877 @end deffn | 3010 @end deffn |
| 3011 @deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF |
| 3012 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. |
| 3013 @end deffn |
2878 @deffn {} BFD_RELOC_MACH_O_PAIR | 3014 @deffn {} BFD_RELOC_MACH_O_PAIR |
2879 Pair of relocation. Contains the first symbol. | 3015 Pair of relocation. Contains the first symbol. |
2880 @end deffn | 3016 @end deffn |
2881 @deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 | 3017 @deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 |
2882 @deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 | 3018 @deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 |
2883 PCREL relocations. They are marked as branch to create PLT entry if | 3019 PCREL relocations. They are marked as branch to create PLT entry if |
2884 required. | 3020 required. |
2885 @end deffn | 3021 @end deffn |
2886 @deffn {} BFD_RELOC_MACH_O_X86_64_GOT | 3022 @deffn {} BFD_RELOC_MACH_O_X86_64_GOT |
2887 Used when referencing a GOT entry. | 3023 Used when referencing a GOT entry. |
(...skipping 109 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2997 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA | 3133 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA |
2998 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA | 3134 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA |
2999 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 | 3135 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 |
3000 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 | 3136 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 |
3001 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 | 3137 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 |
3002 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 | 3138 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 |
3003 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 | 3139 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 |
3004 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 | 3140 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 |
3005 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 | 3141 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 |
3006 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 | 3142 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 |
| 3143 @deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL |
| 3144 @deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD |
| 3145 @deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD |
| 3146 @deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD |
| 3147 @deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD |
| 3148 @deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD |
3007 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD | 3149 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD |
3008 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD | 3150 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD |
3009 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO | 3151 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO |
3010 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO | 3152 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO |
3011 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI | 3153 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI |
3012 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI | 3154 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI |
3013 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA | 3155 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA |
3014 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA | 3156 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA |
3015 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE | 3157 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE |
3016 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE | 3158 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE |
3017 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO | 3159 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO |
3018 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO | 3160 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO |
3019 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI | 3161 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI |
3020 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI | 3162 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI |
3021 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA | 3163 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA |
3022 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA | 3164 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA |
3023 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 | 3165 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 |
3024 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 | 3166 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 |
3025 @deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 | 3167 @deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 |
| 3168 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE |
| 3169 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE |
| 3170 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO |
| 3171 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO |
| 3172 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI |
| 3173 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI |
| 3174 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA |
| 3175 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA |
3026 Tilera TILEPro Relocations. | 3176 Tilera TILEPro Relocations. |
3027 @end deffn | 3177 @end deffn |
3028 @deffn {} BFD_RELOC_TILEGX_HW0 | 3178 @deffn {} BFD_RELOC_TILEGX_HW0 |
3029 @deffnx {} BFD_RELOC_TILEGX_HW1 | 3179 @deffnx {} BFD_RELOC_TILEGX_HW1 |
3030 @deffnx {} BFD_RELOC_TILEGX_HW2 | 3180 @deffnx {} BFD_RELOC_TILEGX_HW2 |
3031 @deffnx {} BFD_RELOC_TILEGX_HW3 | 3181 @deffnx {} BFD_RELOC_TILEGX_HW3 |
3032 @deffnx {} BFD_RELOC_TILEGX_HW0_LAST | 3182 @deffnx {} BFD_RELOC_TILEGX_HW0_LAST |
3033 @deffnx {} BFD_RELOC_TILEGX_HW1_LAST | 3183 @deffnx {} BFD_RELOC_TILEGX_HW1_LAST |
3034 @deffnx {} BFD_RELOC_TILEGX_HW2_LAST | 3184 @deffnx {} BFD_RELOC_TILEGX_HW2_LAST |
3035 @deffnx {} BFD_RELOC_TILEGX_COPY | 3185 @deffnx {} BFD_RELOC_TILEGX_COPY |
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3075 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL | 3225 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL |
3076 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL | 3226 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL |
3077 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL | 3227 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL |
3078 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL | 3228 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL |
3079 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL | 3229 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL |
3080 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL | 3230 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL |
3081 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL | 3231 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL |
3082 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL | 3232 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL |
3083 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT | 3233 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT |
3084 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT | 3234 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT |
3085 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT | |
3086 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT | |
3087 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT | |
3088 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT | |
3089 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT | |
3090 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT | |
3091 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT | 3235 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT |
3092 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT | 3236 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT |
3093 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT | 3237 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT |
3094 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT | 3238 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT |
3095 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT | |
3096 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT | |
3097 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD | 3239 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD |
3098 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD | 3240 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD |
3099 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD | 3241 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE |
3100 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD | 3242 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE |
3101 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD | 3243 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE |
3102 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD | 3244 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE |
3103 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD | 3245 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE |
3104 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD | 3246 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE |
3105 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD | 3247 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD |
3106 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD | 3248 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD |
3107 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD | 3249 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD |
3108 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD | 3250 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD |
3109 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD | |
3110 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD | |
3111 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE | 3251 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE |
3112 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE | 3252 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE |
3113 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE | |
3114 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE | |
3115 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE | |
3116 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE | |
3117 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE | |
3118 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE | |
3119 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE | 3253 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE |
3120 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE | 3254 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE |
3121 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE | 3255 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE |
3122 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE | 3256 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE |
3123 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE | |
3124 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE | |
3125 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 | 3257 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 |
3126 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 | 3258 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 |
3127 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 | 3259 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 |
3128 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 | 3260 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 |
3129 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 | 3261 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 |
3130 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 | 3262 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 |
| 3263 @deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL |
| 3264 @deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD |
| 3265 @deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD |
| 3266 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD |
| 3267 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD |
| 3268 @deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD |
| 3269 @deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD |
| 3270 @deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD |
| 3271 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD |
| 3272 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD |
3131 Tilera TILE-Gx Relocations. | 3273 Tilera TILE-Gx Relocations. |
3132 @end deffn | 3274 @end deffn |
3133 @deffn {} BFD_RELOC_EPIPHANY_SIMM8 | 3275 @deffn {} BFD_RELOC_EPIPHANY_SIMM8 |
3134 Adapteva EPIPHANY - 8 bit signed pc-relative displacement | 3276 Adapteva EPIPHANY - 8 bit signed pc-relative displacement |
3135 @end deffn | 3277 @end deffn |
3136 @deffn {} BFD_RELOC_EPIPHANY_SIMM24 | 3278 @deffn {} BFD_RELOC_EPIPHANY_SIMM24 |
3137 Adapteva EPIPHANY - 24 bit signed pc-relative displacement | 3279 Adapteva EPIPHANY - 24 bit signed pc-relative displacement |
3138 @end deffn | 3280 @end deffn |
3139 @deffn {} BFD_RELOC_EPIPHANY_HIGH | 3281 @deffn {} BFD_RELOC_EPIPHANY_HIGH |
3140 Adapteva EPIPHANY - 16 most-significant bits of absolute address | 3282 Adapteva EPIPHANY - 16 most-significant bits of absolute address |
(...skipping 71 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3212 (bfd *, struct bfd_link_info *); | 3354 (bfd *, struct bfd_link_info *); |
3213 @end example | 3355 @end example |
3214 @strong{Description}@* | 3356 @strong{Description}@* |
3215 Provides default handling for relaxing for back ends which | 3357 Provides default handling for relaxing for back ends which |
3216 don't do section gc -- i.e., does nothing. | 3358 don't do section gc -- i.e., does nothing. |
3217 | 3359 |
3218 @findex bfd_generic_lookup_section_flags | 3360 @findex bfd_generic_lookup_section_flags |
3219 @subsubsection @code{bfd_generic_lookup_section_flags} | 3361 @subsubsection @code{bfd_generic_lookup_section_flags} |
3220 @strong{Synopsis} | 3362 @strong{Synopsis} |
3221 @example | 3363 @example |
3222 void bfd_generic_lookup_section_flags | 3364 bfd_boolean bfd_generic_lookup_section_flags |
3223 (struct bfd_link_info *, struct flag_info *); | 3365 (struct bfd_link_info *, struct flag_info *, asection *); |
3224 @end example | 3366 @end example |
3225 @strong{Description}@* | 3367 @strong{Description}@* |
3226 Provides default handling for section flags lookup | 3368 Provides default handling for section flags lookup |
3227 -- i.e., does nothing. | 3369 -- i.e., does nothing. |
| 3370 Returns FALSE if the section should be omitted, otherwise TRUE. |
3228 | 3371 |
3229 @findex bfd_generic_merge_sections | 3372 @findex bfd_generic_merge_sections |
3230 @subsubsection @code{bfd_generic_merge_sections} | 3373 @subsubsection @code{bfd_generic_merge_sections} |
3231 @strong{Synopsis} | 3374 @strong{Synopsis} |
3232 @example | 3375 @example |
3233 bfd_boolean bfd_generic_merge_sections | 3376 bfd_boolean bfd_generic_merge_sections |
3234 (bfd *, struct bfd_link_info *); | 3377 (bfd *, struct bfd_link_info *); |
3235 @end example | 3378 @end example |
3236 @strong{Description}@* | 3379 @strong{Description}@* |
3237 Provides default handling for SEC_MERGE section merging for back ends | 3380 Provides default handling for SEC_MERGE section merging for back ends |
3238 which don't have SEC_MERGE support -- i.e., does nothing. | 3381 which don't have SEC_MERGE support -- i.e., does nothing. |
3239 | 3382 |
3240 @findex bfd_generic_get_relocated_section_contents | 3383 @findex bfd_generic_get_relocated_section_contents |
3241 @subsubsection @code{bfd_generic_get_relocated_section_contents} | 3384 @subsubsection @code{bfd_generic_get_relocated_section_contents} |
3242 @strong{Synopsis} | 3385 @strong{Synopsis} |
3243 @example | 3386 @example |
3244 bfd_byte *bfd_generic_get_relocated_section_contents | 3387 bfd_byte *bfd_generic_get_relocated_section_contents |
3245 (bfd *abfd, | 3388 (bfd *abfd, |
3246 struct bfd_link_info *link_info, | 3389 struct bfd_link_info *link_info, |
3247 struct bfd_link_order *link_order, | 3390 struct bfd_link_order *link_order, |
3248 bfd_byte *data, | 3391 bfd_byte *data, |
3249 bfd_boolean relocatable, | 3392 bfd_boolean relocatable, |
3250 asymbol **symbols); | 3393 asymbol **symbols); |
3251 @end example | 3394 @end example |
3252 @strong{Description}@* | 3395 @strong{Description}@* |
3253 Provides default handling of relocation effort for back ends | 3396 Provides default handling of relocation effort for back ends |
3254 which can't be bothered to do it efficiently. | 3397 which can't be bothered to do it efficiently. |
3255 | 3398 |
OLD | NEW |