Changes from 3.7 merge to files not in upstream

test/NaCl/ARM/neon-vld4-sandboxing.ll

Index: test/NaCl/ARM/neon-vld4-sandboxing.ll
diff --git a/test/NaCl/ARM/neon-vld4-sandboxing.ll b/test/NaCl/ARM/neon-vld4-sandboxing.ll
index 096146b51d597952dcf92129f3a3ce3c3bad8567..50576a6bf3a10acc5564cdef537ed6ca6fb3f044 100644
--- a/test/NaCl/ARM/neon-vld4-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld4-sandboxing.ll
@@ -28,7 +28,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
   %tmp4 = add <8 x i8> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld4.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:64]
   ret <8 x i8> %tmp4
 }
@@ -39,7 +39,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
   %tmp4 = add <4 x i16> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld4.16 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:128]
   ret <4 x i16> %tmp4
 }
@@ -50,7 +50,7 @@ define <2 x i32> @vld4i32(i32* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
   %tmp4 = add <2 x i32> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld4.32 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:256]
   ret <2 x i32> %tmp4
 }
@@ -61,7 +61,7 @@ define <1 x i64> @vld4i64(i64* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
   %tmp4 = add <1 x i64> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:256]
   ret <1 x i64> %tmp4
 }
@@ -71,36 +71,36 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
   %tmp4 = add <16 x i8> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld4.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:256]!
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld4.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:256]
   ret <16 x i8> %tmp4
 }
 
 define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
-  %A = load i8** %ptr
+  %A = load i8*, i8** %ptr
   %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
-; CHECK:         bic r2, r2, #3221225472
+; CHECK:         bic r2, r2, #-1073741824
 ; CHECK-NEXT:    vld4.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r2:128], r1
   %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
   %tmp4 = add <8 x i8> %tmp2, %tmp3
-  %tmp5 = getelementptr i8* %A, i32 %inc
+  %tmp5 = getelementptr i8, i8* %A, i32 %inc
   store i8* %tmp5, i8** %ptr
   ret <8 x i8> %tmp4
 }
 
 define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
-  %A = load i16** %ptr
+  %A = load i16*, i16** %ptr
   %tmp0 = bitcast i16* %A to i8*
   %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
-; CHECK:         bic r1, r1, #3221225472
+; CHECK:         bic r1, r1, #-1073741824
 ; CHECK-NEXT:    vld4.16 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r1:64]!
   %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
   %tmp4 = add <8 x i16> %tmp2, %tmp3
-  %tmp5 = getelementptr i16* %A, i32 32
+  %tmp5 = getelementptr i16, i16* %A, i32 32
   store i16* %tmp5, i16** %ptr
   ret <8 x i16> %tmp4
 }