Changes from 3.7 merge to files not in upstream

test/NaCl/ARM/neon-vld3-sandboxing.ll

Index: test/NaCl/ARM/neon-vld3-sandboxing.ll
diff --git a/test/NaCl/ARM/neon-vld3-sandboxing.ll b/test/NaCl/ARM/neon-vld3-sandboxing.ll
index 7e1e9778247fd9d654afc3ff97ccdcc298dcf31e..200b04b8c1f2a069cc5f6477f18e59306e82714f 100644
--- a/test/NaCl/ARM/neon-vld3-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld3-sandboxing.ll
@@ -28,7 +28,7 @@ define <8 x i8> @vld3i8(i32 %foobar, i32 %ba, i8* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
   %tmp4 = add <8 x i8> %tmp2, %tmp3
-; CHECK:         bic r2, r2, #3221225472
+; CHECK:         bic r2, r2, #-1073741824
 ; CHECK-NEXT:    vld3.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r2:64]
   ret <8 x i8> %tmp4
 }
@@ -39,7 +39,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
   %tmp4 = add <4 x i16> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld3.16 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0]
   ret <4 x i16> %tmp4
 }
@@ -50,7 +50,7 @@ define <2 x i32> @vld3i32(i32* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2
   %tmp4 = add <2 x i32> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld3.32 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0]
   ret <2 x i32> %tmp4
 }
@@ -61,7 +61,7 @@ define <1 x i64> @vld3i64(i64* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
   %tmp4 = add <1 x i64> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld1.64 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:64]
   ret <1 x i64> %tmp4
 }
@@ -71,35 +71,35 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwind {
   %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
   %tmp4 = add <16 x i8> %tmp2, %tmp3
-; CHECK:         bic r0, r0, #3221225472
+; CHECK:         bic r0, r0, #-1073741824
 ; CHECK-NEXT:    vld3.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r0:64]!
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
-  %A = load i16** %ptr
+  %A = load i16*, i16** %ptr
   %tmp0 = bitcast i16* %A to i8*
   %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
-; CHECK:         bic r2, r2, #3221225472
+; CHECK:         bic r2, r2, #-1073741824
 ; CHECK-NEXT:    vld3.16  {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r2], r1
   %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
   %tmp4 = add <4 x i16> %tmp2, %tmp3
-  %tmp5 = getelementptr i16* %A, i32 %inc
+  %tmp5 = getelementptr i16, i16* %A, i32 %inc
   store i16* %tmp5, i16** %ptr
   ret <4 x i16> %tmp4
 }
 
 define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
-  %A = load i32** %ptr
+  %A = load i32*, i32** %ptr
   %tmp0 = bitcast i32* %A to i8*
   %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1)
-; CHECK:         bic r1, r1, #3221225472
+; CHECK:         bic r1, r1, #-1073741824
 ; CHECK-NEXT:    vld3.32  {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r1]!
   %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
   %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
   %tmp4 = add <4 x i32> %tmp2, %tmp3
-  %tmp5 = getelementptr i32* %A, i32 12
+  %tmp5 = getelementptr i32, i32* %A, i32 12
   store i32* %tmp5, i32** %ptr
   ret <4 x i32> %tmp4
 }