MIPS: Add float instructions and test coverage, part two

src/mips/disasm-mips.cc

Index: src/mips/disasm-mips.cc
diff --git a/src/mips/disasm-mips.cc b/src/mips/disasm-mips.cc
index 32dffff1d2945212a8d81997f997980ce3cc21ae..f68876456e1f174c9d954930dc07ed921dda1b13 100644
--- a/src/mips/disasm-mips.cc
+++ b/src/mips/disasm-mips.cc
@@ -581,6 +581,9 @@ bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
     case CEIL_W_D:
       Format(instr, "ceil.w.'t 'fd, 'fs");
       break;
+    case CLASS_D:
+      Format(instr, "class.'t 'fd, 'fs");
+      break;
     case CEIL_L_D:
       Format(instr, "ceil.l.'t 'fd, 'fs");
       break;
@@ -647,6 +650,9 @@ void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
     case CVT_S_L:
       Format(instr, "cvt.s.l 'fd, 'fs");
       break;
+    case CMP_AF:
+      Format(instr, "cmp.af.d  'fd,  'fs, 'ft");
+      break;
     case CMP_UN:
       Format(instr, "cmp.un.d  'fd,  'fs, 'ft");
       break;
@@ -950,6 +956,14 @@ void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
       }
       break;
     }
+    case BITSWAP: {
+      if (IsMipsArchVariant(kMips32r6)) {
+        Format(instr, "bitswap 'rd, 'rt");
+      } else {
+        Unknown(instr);
+      }
+      break;
+    }
     default:
       UNREACHABLE();
   }