Remove tst+ldr, tst+str from checked-in nexes.

src/trusted/validator_arm/testdata/test_stores.S

Index: src/trusted/validator_arm/testdata/test_stores.S
diff --git a/src/trusted/validator_arm/testdata/test_stores.S b/src/trusted/validator_arm/testdata/test_stores.S
index 2be3ce4c492368f20494abe2ce96b0b639b3b389..40473d45c39e00b654003993277cc94d757345d7 100644
--- a/src/trusted/validator_arm/testdata/test_stores.S
+++ b/src/trusted/validator_arm/testdata/test_stores.S
@@ -59,16 +59,3 @@ bundle6:
   str r1, [sp], r2        @ post-indexing sp by a register is an ERROR
   bic r0, r0, #0xC0000000 @ Mask a register, and
   str r1, [r0, r2]        @ use it in register pre-index store: ERROR
-
-conditional_sandbox:
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  streq r1, [r0]          @ store: should work.
-
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  str r1, [r0]            @ store unconditionally: ERROR.
-
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  strgt r1, [r0]          @ store using wrong predicate: ERROR.
-
-  tsteq r0, #0xC0000000   @ Conditionally set Z if the top two bits are clear,
-  strgt r1, [r0]          @ and store using wrong predicate: ERROR.