Remove tst+ldr, tst+str from checked-in nexes.

src/trusted/validator_arm/testdata/test_stores.S

 @ Copyright (c) 2011 The Native Client Authors. All rights reserved.
 @ Use of this source code is governed by a BSD-style license that can be
 @ found in the LICENSE file.
 
 @
 @ Tests both legal and illegal variations on stores -- both stores that
 @ require masking, and stores that are guaranteed sandboxed (i.e. through SP)
 @
 
 @ we restrict store to the lower 1GB of the address space
@@ skipping 41 matching lines @@
   bic r0, r0, #0xC0000000 @ Mask a register, and
   str r1, [r0], r2        @ use it in register post-index store: should pass.
   nop                     @ Don't mask, and
   str r1, [r0], r2        @ use it in register post-index store: ERROR.
 
 bundle6:
   str r1, [sp], #1024     @ post-indexing sp by a constant is OK
   str r1, [sp], r2        @ post-indexing sp by a register is an ERROR
   bic r0, r0, #0xC0000000 @ Mask a register, and
   str r1, [r0, r2]        @ use it in register pre-index store: ERROR
-
-conditional_sandbox:
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  streq r1, [r0]          @ store: should work.
-
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  str r1, [r0]            @ store unconditionally: ERROR.
-
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  strgt r1, [r0]          @ store using wrong predicate: ERROR.
-
-  tsteq r0, #0xC0000000   @ Conditionally set Z if the top two bits are clear,
-  strgt r1, [r0]          @ and store using wrong predicate: ERROR.