Index: src/arm/assembler-arm.cc |
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc |
index 80abafdefa348addcb241a14c0871dc207d488b5..b14515ae1309b64b1a2fde29267337b94e2d4ff4 100644 |
--- a/src/arm/assembler-arm.cc |
+++ b/src/arm/assembler-arm.cc |
@@ -2392,6 +2392,24 @@ void Assembler::vmul(const DwVfpRegister dst, |
} |
+void Assembler::vmla(const DwVfpRegister dst, |
+ const DwVfpRegister src1, |
+ const DwVfpRegister src2, |
+ const Condition cond) { |
+ // Instruction details available in ARM DDI 0406C.b, A8-892. |
+ // cond(31-28) | 11100(27-23) | D=?(22) | 00(21-20) | Vn(19-16) | |
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | N=?(7) | op(6)=0 | M=?(5) | 0(4) | |
+ // Vm(3-0) |
+ // |
+ // We leave D, N and M implicit zero, just like vmul. |
+ // op=0 means VMLA, as opposed to VMLS. |
+ // FIXME: Clean up comments. |
+ unsigned x = (cond | 0x1C*B23 | src1.code()*B16 | |
+ dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
+ emit(x); |
+} |
+ |
+ |
void Assembler::vdiv(const DwVfpRegister dst, |
const DwVfpRegister src1, |
const DwVfpRegister src2, |