OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
(...skipping 2374 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2385 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. | 2385 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
2386 // Instruction details available in ARM DDI 0406A, A8-784. | 2386 // Instruction details available in ARM DDI 0406A, A8-784. |
2387 // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) | | 2387 // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) | |
2388 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) | 2388 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
2389 ASSERT(CpuFeatures::IsEnabled(VFP2)); | 2389 ASSERT(CpuFeatures::IsEnabled(VFP2)); |
2390 emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 | | 2390 emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 | |
2391 dst.code()*B12 | 0x5*B9 | B8 | src2.code()); | 2391 dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
2392 } | 2392 } |
2393 | 2393 |
2394 | 2394 |
| 2395 void Assembler::vmla(const DwVfpRegister dst, |
| 2396 const DwVfpRegister src1, |
| 2397 const DwVfpRegister src2, |
| 2398 const Condition cond) { |
| 2399 // Instruction details available in ARM DDI 0406C.b, A8-892. |
| 2400 // cond(31-28) | 11100(27-23) | D=?(22) | 00(21-20) | Vn(19-16) | |
| 2401 // Vd(15-12) | 101(11-9) | sz(8)=1 | N=?(7) | op(6)=0 | M=?(5) | 0(4) | |
| 2402 // Vm(3-0) |
| 2403 // |
| 2404 // We leave D, N and M implicit zero, just like vmul. |
| 2405 // op=0 means VMLA, as opposed to VMLS. |
| 2406 // FIXME: Clean up comments. |
| 2407 unsigned x = (cond | 0x1C*B23 | src1.code()*B16 | |
| 2408 dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2409 emit(x); |
| 2410 } |
| 2411 |
| 2412 |
2395 void Assembler::vdiv(const DwVfpRegister dst, | 2413 void Assembler::vdiv(const DwVfpRegister dst, |
2396 const DwVfpRegister src1, | 2414 const DwVfpRegister src1, |
2397 const DwVfpRegister src2, | 2415 const DwVfpRegister src2, |
2398 const Condition cond) { | 2416 const Condition cond) { |
2399 // Dd = vdiv(Dn, Dm) double precision floating point division. | 2417 // Dd = vdiv(Dn, Dm) double precision floating point division. |
2400 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. | 2418 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
2401 // Instruction details available in ARM DDI 0406A, A8-584. | 2419 // Instruction details available in ARM DDI 0406A, A8-584. |
2402 // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) | | 2420 // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) | |
2403 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0) | 2421 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
2404 ASSERT(CpuFeatures::IsEnabled(VFP2)); | 2422 ASSERT(CpuFeatures::IsEnabled(VFP2)); |
(...skipping 367 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2772 | 2790 |
2773 // Since a constant pool was just emitted, move the check offset forward by | 2791 // Since a constant pool was just emitted, move the check offset forward by |
2774 // the standard interval. | 2792 // the standard interval. |
2775 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 2793 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
2776 } | 2794 } |
2777 | 2795 |
2778 | 2796 |
2779 } } // namespace v8::internal | 2797 } } // namespace v8::internal |
2780 | 2798 |
2781 #endif // V8_TARGET_ARCH_ARM | 2799 #endif // V8_TARGET_ARCH_ARM |
OLD | NEW |