WIP Atomics

src/compiler/x64/instruction-selector-x64.cc

Index: src/compiler/x64/instruction-selector-x64.cc
diff --git a/src/compiler/x64/instruction-selector-x64.cc b/src/compiler/x64/instruction-selector-x64.cc
index 26d8960b913f897c458f9de1ba0cad07959786d4..1038cc3d1c59894715f0674750b6b45eb4958be4 100644
--- a/src/compiler/x64/instruction-selector-x64.cc
+++ b/src/compiler/x64/instruction-selector-x64.cc
@@ -146,6 +146,47 @@ void InstructionSelector::VisitLoad(Node* node) {
 }
 
 
+void InstructionSelector::VisitLoadAtomic(Node* node) {
+  MachineType rep = RepresentationOf(OpParameter<LoadRepresentation>(node));
+  MachineType typ = TypeOf(OpParameter<LoadRepresentation>(node));
+  X64OperandGenerator g(this);
+
+  ArchOpcode opcode;
+  switch (rep) {
+    case kRepFloat32:
+      opcode = kX64Movss;
+      break;
+    case kRepFloat64:
+      opcode = kX64Movsd;
+      break;
+    case kRepBit:  // Fall through.
+    case kRepWord8:
+      opcode = typ == kTypeInt32 ? kX64Movsxbl : kX64Movzxbl;
+      break;
+    case kRepWord16:
+      opcode = typ == kTypeInt32 ? kX64Movsxwl : kX64Movzxwl;
+      break;
+    case kRepWord32:
+      opcode = kX64Movl;
+      break;
+    case kRepTagged:
+    case kRepWord64:
+    default:
+      UNREACHABLE();
+      return;
+  }
+
+  InstructionOperand outputs[1];
+  outputs[0] = g.DefineAsRegister(node);
+  InstructionOperand inputs[3];
+  size_t input_count = 0;
+  AddressingMode mode =
+      g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count);
+  InstructionCode code = opcode | AddressingModeField::encode(mode);
+  Emit(code, 1, outputs, input_count, inputs);
+}
+
+
 void InstructionSelector::VisitStore(Node* node) {
   X64OperandGenerator g(this);
   Node* base = node->InputAt(0);