Improve page flag checking sequence on ARM.

src/arm/macro-assembler-arm.cc

Index: src/arm/macro-assembler-arm.cc
diff --git a/src/arm/macro-assembler-arm.cc b/src/arm/macro-assembler-arm.cc
index cc7fc4d3a4203706ce0a9cccee63e43d2adbdbb2..cf95e77f0771c346e28c31943a50f0861dae587b 100644
--- a/src/arm/macro-assembler-arm.cc
+++ b/src/arm/macro-assembler-arm.cc
@@ -3497,7 +3497,8 @@ void MacroAssembler::CheckPageFlag(
     int mask,
     Condition cc,
     Label* condition_met) {
-  and_(scratch, object, Operand(~Page::kPageAlignmentMask));
+  Move(scratch, object);

[Please use jfb - chromium.org, 2012/10/09 13:09:21]

Actually, let me retract my LGTM: this will generate an extra move on non-ARMv7
machines. The move should be emitted with the same condition as Bfc:
if (!CpuFeatures::IsSupported(ARMv7) || predictable_code_size())

[Michael Starzinger, 2012/10/09 13:36:20]

Done. You are right, I totally missed that.

+  Bfc(scratch, 0, kPageSizeBits);

[m.m.capewell, 2012/10/09 13:25:27]

A more generic way of doing this, possibly with slightly better performance, is
using two shifts, right then left, by kPageSizeBits.

[Michael Starzinger, 2012/10/09 13:54:34]

So just to clarify. Do you think that the two-shift-approach would perform
better than move+bfc on ARMv7? That would surprise me, but I am no ARM expert.

My approach would be to always use move+bfc on ARMv7 and only use the
two-shift-approach when we are running on non-ARMv7 and (lsb == 0). Need to find
a non-ARMv7 device for measurements.

   ldr(scratch, MemOperand(scratch, MemoryChunk::kFlagsOffset));
   tst(scratch, Operand(mask));
   b(cc, condition_met);