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Unified Diff: src/trusted/validator_ragel/gen/decoder_x86_64.c

Issue 11000033: Move validator_x86_XX.rl out of unreviewed. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 2 months ago
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Index: src/trusted/validator_ragel/gen/decoder_x86_64.c
===================================================================
--- src/trusted/validator_ragel/gen/decoder_x86_64.c (revision 9911)
+++ src/trusted/validator_ragel/gen/decoder_x86_64.c (working copy)
@@ -11,7 +11,7 @@
#include "native_client/src/include/elf32.h"
#include "native_client/src/shared/utils/types.h"
-#include "native_client/src/trusted/validator_ragel/unreviewed/decoding.h"
+#include "native_client/src/trusted/validator_ragel/decoder_internal.h"
#include "native_client/src/trusted/validator_ragel/gen/decoder_x86_64_instruction_consts.h"
@@ -9498,7 +9498,7 @@
136u, 143u, 144u, 151u, 152u, 159u, 160u, 167u,
168u, 175u, 176u, 183u, 184u, 191u, 192u, 199u,
200u, 207u, 208u, 215u, 216u, 223u, 224u, 231u,
- 240u, 247u, 248u, 255u, 4u, 5u, 12u, 13u,
+ 232u, 239u, 248u, 255u, 4u, 5u, 12u, 13u,
20u, 21u, 28u, 29u, 36u, 37u, 44u, 45u,
52u, 53u, 60u, 61u, 68u, 76u, 84u, 92u,
100u, 108u, 116u, 124u, 132u, 140u, 148u, 156u,
@@ -9629,8 +9629,8 @@
80u, 87u, 88u, 95u, 96u, 103u, 104u, 111u,
112u, 119u, 120u, 127u, 128u, 135u, 136u, 143u,
144u, 151u, 152u, 159u, 160u, 167u, 168u, 175u,
- 176u, 183u, 184u, 191u, 192u, 199u, 200u, 207u,
- 208u, 215u, 216u, 223u, 224u, 231u, 232u, 239u,
+ 176u, 183u, 184u, 191u, 192u, 199u, 208u, 215u,
+ 216u, 223u, 224u, 231u, 232u, 239u, 240u, 247u,
248u, 255u, 4u, 5u, 20u, 21u, 28u, 29u,
36u, 37u, 44u, 45u, 52u, 53u, 60u, 61u,
68u, 84u, 92u, 100u, 108u, 116u, 124u, 132u,
@@ -9847,8 +9847,8 @@
119u, 120u, 127u, 128u, 135u, 136u, 143u, 144u,
151u, 152u, 159u, 160u, 167u, 168u, 175u, 176u,
183u, 184u, 191u, 192u, 199u, 200u, 207u, 208u,
- 215u, 216u, 223u, 224u, 231u, 232u, 239u, 240u,
- 247u, 4u, 5u, 12u, 13u, 20u, 21u, 28u,
+ 215u, 216u, 223u, 224u, 231u, 232u, 239u, 248u,
+ 255u, 4u, 5u, 12u, 13u, 20u, 21u, 28u,
29u, 36u, 37u, 44u, 45u, 52u, 53u, 60u,
61u, 68u, 76u, 84u, 92u, 100u, 108u, 116u,
124u, 132u, 140u, 148u, 156u, 164u, 172u, 180u,
@@ -9859,7 +9859,7 @@
127u, 128u, 135u, 136u, 143u, 144u, 151u, 152u,
159u, 160u, 167u, 168u, 175u, 176u, 183u, 184u,
191u, 192u, 199u, 200u, 207u, 208u, 215u, 216u,
- 223u, 224u, 231u, 232u, 239u, 240u, 247u, 4u,
+ 223u, 232u, 239u, 240u, 247u, 248u, 255u, 4u,
5u, 12u, 13u, 20u, 21u, 28u, 29u, 36u,
37u, 44u, 45u, 68u, 76u, 84u, 92u, 100u,
108u, 132u, 140u, 148u, 156u, 164u, 172u, 0u,
@@ -10838,7 +10838,7 @@
87u, 88u, 95u, 96u, 103u, 104u, 111u, 112u,
119u, 120u, 127u, 128u, 135u, 136u, 143u, 144u,
151u, 152u, 159u, 160u, 167u, 168u, 175u, 176u,
- 183u, 184u, 191u, 200u, 207u, 208u, 215u, 216u,
+ 183u, 184u, 191u, 192u, 199u, 208u, 215u, 216u,
223u, 224u, 231u, 232u, 239u, 240u, 247u, 248u,
255u, 192u, 239u, 4u, 5u, 68u, 132u, 0u,
7u, 64u, 71u, 128u, 135u, 192u, 199u, 4u,
@@ -23580,8 +23580,8 @@
1771, 1716, 1719, 1722, 1725, 1728, 1731, 1734,
1737, 1740, 1742, 1744, 1746, 1748, 1750, 1752,
1754, 1756, 1758, 1760, 1762, 1764, 1766, 1768,
- 1770, 1772, 1773, 1774, 1775, 1776, 1778, 1779,
- 1777, 1781, 1782, 1784, 1785, 1787, 1788, 1790,
+ 1770, 1772, 1773, 1774, 1775, 1776, 1777, 1779,
+ 1778, 1781, 1782, 1784, 1785, 1787, 1788, 1790,
1791, 1793, 1794, 1796, 1797, 1799, 1800, 1802,
1803, 1805, 1807, 1809, 1811, 1813, 1815, 1817,
1819, 1821, 1823, 1825, 1827, 1829, 1831, 1833,
@@ -23680,8 +23680,8 @@
2345, 2347, 2349, 2351, 2296, 2299, 2302, 2305,
2308, 2311, 2314, 2317, 2320, 2322, 2324, 2326,
2328, 2330, 2332, 2334, 2336, 2338, 2340, 2342,
- 2344, 2346, 2348, 2350, 2352, 2353, 2354, 2355,
- 2356, 2357, 2359, 2358, 2361, 2362, 2364, 2365,
+ 2344, 2346, 2348, 2350, 2352, 2354, 2355, 2356,
+ 2357, 2358, 2359, 2353, 2361, 2362, 2364, 2365,
2367, 2368, 2370, 2371, 2373, 2374, 2376, 2377,
2379, 2380, 2382, 2384, 2386, 2388, 2390, 2392,
2394, 2396, 2398, 2400, 2402, 2404, 2406, 2408,
@@ -23849,7 +23849,7 @@
3178, 3181, 3184, 3187, 3190, 3193, 3196, 3198,
3200, 3202, 3204, 3206, 3208, 3210, 3212, 3214,
3216, 3218, 3220, 3222, 3224, 3226, 3228, 3229,
- 3230, 3231, 3232, 3233, 3234, 3235, 3237, 3238,
+ 3230, 3231, 3232, 3233, 3235, 3234, 3237, 3238,
3240, 3241, 3243, 3244, 3246, 3247, 3249, 3250,
3252, 3253, 3255, 3256, 3258, 3259, 3261, 3263,
3265, 3267, 3269, 3271, 3273, 3275, 3277, 3279,
@@ -23857,7 +23857,7 @@
3242, 3245, 3248, 3251, 3254, 3257, 3260, 3262,
3264, 3266, 3268, 3270, 3272, 3274, 3276, 3278,
3280, 3282, 3284, 3286, 3288, 3290, 3292, 3293,
- 3294, 3295, 3296, 3297, 3298, 3299, 1909, 1910,
+ 3294, 3295, 3297, 3298, 3299, 3296, 1909, 1910,
1909, 1910, 1909, 1910, 1909, 1910, 1909, 1910,
1909, 1910, 1912, 1912, 1912, 1912, 1912, 1912,
1914, 1914, 1914, 1914, 1914, 1914, 1908, 1911,
@@ -24773,8 +24773,8 @@
5415, 5360, 5363, 5366, 5369, 5372, 5375, 5378,
5381, 5384, 5386, 5388, 5390, 5392, 5394, 5396,
5398, 5400, 5402, 5404, 5406, 5408, 5410, 5412,
- 5414, 5417, 5418, 5419, 5420, 5421, 5422, 5423,
- 5416, 5424, 34, 5426, 5427, 5429, 5431, 5425,
+ 5414, 5416, 5418, 5419, 5420, 5421, 5422, 5423,
+ 5417, 5424, 34, 5426, 5427, 5429, 5431, 5425,
5428, 5430, 5432, 34, 5434, 5435, 5437, 5438,
5440, 5441, 5443, 5444, 5446, 5447, 5449, 5450,
5452, 5453, 5455, 5457, 5459, 5461, 5463, 5465,
@@ -39561,65 +39561,18 @@
-#define GET_REX_PREFIX() instruction.prefix.rex
-#define SET_REX_PREFIX(P) instruction.prefix.rex = (P)
-#define GET_VEX_PREFIX2() vex_prefix2
-#define SET_VEX_PREFIX2(P) vex_prefix2 = (P)
-#define GET_VEX_PREFIX3() vex_prefix3
-#define SET_VEX_PREFIX3(P) vex_prefix3 = (P)
-#define SET_DATA16_PREFIX(S) instruction.prefix.data16 = (S)
-#define SET_LOCK_PREFIX(S) instruction.prefix.lock = (S)
-#define SET_REPZ_PREFIX(S) instruction.prefix.repz = (S)
-#define SET_REPNZ_PREFIX(S) instruction.prefix.repnz = (S)
-#define SET_BRANCH_TAKEN(S) instruction.prefix.branch_taken = (S)
-#define SET_BRANCH_NOT_TAKEN(S) instruction.prefix.branch_not_taken = (S)
-#define SET_INSTRUCTION_NAME(N) instruction.name = (N)
-#define GET_OPERAND_NAME(N) instruction.operands[(N)].name
-#define SET_OPERAND_NAME(N, S) instruction.operands[(N)].name = (S)
-#define SET_OPERAND_TYPE(N, S) instruction.operands[(N)].type = (S)
-#define SET_OPERANDS_COUNT(N) instruction.operands_count = (N)
-#define SET_MODRM_BASE(N) instruction.rm.base = (N)
-#define SET_MODRM_INDEX(N) instruction.rm.index = (N)
-#define SET_MODRM_SCALE(S) instruction.rm.scale = (S)
-#define SET_DISP_TYPE(T) instruction.rm.disp_type = (T)
-#define SET_DISP_PTR(P) disp = (P)
-#define SET_IMM_TYPE(T) imm_operand = (T)
-#define SET_IMM_PTR(P) imm = (P)
-#define SET_IMM2_TYPE(T) imm2_operand = (T)
-#define SET_IMM2_PTR(P) imm2 = (P)
-#define SET_CPU_FEATURE(F)
-
-enum {
- REX_B = 1,
- REX_X = 2,
- REX_R = 4,
- REX_W = 8
-};
-
-enum imm_mode {
- IMMNONE,
- IMM2,
- IMM8,
- IMM16,
- IMM32,
- IMM64
-};
-
int DecodeChunkAMD64(const uint8_t *data, size_t size,
- process_instruction_func process_instruction,
- process_decoding_error_func process_error,
+ ProcessInstructionFunc process_instruction,
+ ProcessDecodingErrorFunc process_error,
void *userdata) {
const uint8_t *current_position = data;
const uint8_t *end_of_data = data + size;
- const uint8_t *disp = NULL;
- const uint8_t *imm = NULL;
- const uint8_t *imm2 = NULL;
const uint8_t *instruction_start = current_position;
uint8_t vex_prefix2 = 0xe0;
uint8_t vex_prefix3 = 0x00;
- enum imm_mode imm_operand = IMMNONE;
- enum imm_mode imm2_operand = IMMNONE;
- struct instruction instruction;
+ enum ImmediateMode imm_operand = IMMNONE;
+ enum ImmediateMode imm2_operand = IMMNONE;
+ struct Instruction instruction;
int result = TRUE;
int current_state;
@@ -39883,183 +39836,183 @@
{ SET_OPERANDS_COUNT(5); }
break;
case 30:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_16_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_16_BIT); }
break;
case 31:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_8_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_8_BIT); }
break;
case 32:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_32_BIT); }
break;
case 33:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_64_BIT); }
break;
case 34:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_128_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_128_BIT); }
break;
case 35:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_256_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_256_BIT); }
break;
case 36:
- { SET_OPERAND_TYPE(0, OPERAND_CONTROL_REGISTER); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_CONTROL_REGISTER); }
break;
case 37:
- { SET_OPERAND_TYPE(0, OPERAND_DEBUG_REGISTER); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_DEBUG_REGISTER); }
break;
case 38:
- { SET_OPERAND_TYPE(0, OPERAND_FAR_PTR); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_FAR_PTR); }
break;
case 39:
- { SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_32_BIT); }
break;
case 40:
- { SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_64_BIT); }
break;
case 41:
- { SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_80_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_80_BIT); }
break;
case 42:
- { SET_OPERAND_TYPE(0, OPERAND_MMX); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_MMX); }
break;
case 43:
- { SET_OPERAND_TYPE(0, OPERAND_SEGMENT_REGISTER); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_SEGMENT_REGISTER); }
break;
case 44:
- { SET_OPERAND_TYPE(0, OPERAND_SELECTOR); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_SELECTOR); }
break;
case 45:
- { SET_OPERAND_TYPE(0, OPERAND_ST); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_ST); }
break;
case 46:
- { SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_16_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_16_BIT); }
break;
case 47:
- { SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_32_BIT); }
break;
case 48:
- { SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_64_BIT); }
break;
case 49:
- { SET_OPERAND_TYPE(0, OPERAND_X87_BCD); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_BCD); }
break;
case 50:
- { SET_OPERAND_TYPE(0, OPERAND_X87_ENV); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_ENV); }
break;
case 51:
{
- SET_OPERAND_TYPE(0, OPERAND_X87_MMX_MM_STATE);
+ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_MMX_XMM_STATE);
}
break;
case 52:
- { SET_OPERAND_TYPE(0, OPERAND_X87_STATE); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_STATE); }
break;
case 53:
- { SET_OPERAND_TYPE(0, OPERAND_XMM); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_XMM); }
break;
case 54:
- { SET_OPERAND_TYPE(0, OPERAND_YMM); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_YMM); }
break;
case 55:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_8_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_8_BIT); }
break;
case 56:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_16_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_16_BIT); }
break;
case 57:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_32_BIT); }
break;
case 58:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_64_BIT); }
break;
case 59:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_128_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_128_BIT); }
break;
case 60:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_256_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_256_BIT); }
break;
case 61:
- { SET_OPERAND_TYPE(1, OPERAND_CONTROL_REGISTER); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_CONTROL_REGISTER); }
break;
case 62:
- { SET_OPERAND_TYPE(1, OPERAND_DEBUG_REGISTER); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_DEBUG_REGISTER); }
break;
case 63:
- { SET_OPERAND_TYPE(1, OPERAND_FAR_PTR); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_FAR_PTR); }
break;
case 64:
- { SET_OPERAND_TYPE(1, OPERAND_FLOAT_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_FLOAT_32_BIT); }
break;
case 65:
- { SET_OPERAND_TYPE(1, OPERAND_FLOAT_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_FLOAT_64_BIT); }
break;
case 66:
- { SET_OPERAND_TYPE(1, OPERAND_MMX); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_MMX); }
break;
case 67:
- { SET_OPERAND_TYPE(1, OPERAND_SEGMENT_REGISTER); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_SEGMENT_REGISTER); }
break;
case 68:
- { SET_OPERAND_TYPE(1, OPERAND_ST); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_ST); }
break;
case 69:
- { SET_OPERAND_TYPE(1, OPERAND_XMM); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_XMM); }
break;
case 70:
- { SET_OPERAND_TYPE(1, OPERAND_YMM); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_YMM); }
break;
case 71:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_8_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_8_BIT); }
break;
case 72:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_16_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_16_BIT); }
break;
case 73:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_32_BIT); }
break;
case 74:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_64_BIT); }
break;
case 75:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_128_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_128_BIT); }
break;
case 76:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_256_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_256_BIT); }
break;
case 77:
- { SET_OPERAND_TYPE(2, OPERAND_FLOAT_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_FLOAT_32_BIT); }
break;
case 78:
- { SET_OPERAND_TYPE(2, OPERAND_FLOAT_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_FLOAT_64_BIT); }
break;
case 79:
- { SET_OPERAND_TYPE(2, OPERAND_XMM); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_XMM); }
break;
case 80:
- { SET_OPERAND_TYPE(2, OPERAND_YMM); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_YMM); }
break;
case 81:
- { SET_OPERAND_TYPE(3, OPERAND_SIZE_8_BIT); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_8_BIT); }
break;
case 82:
- { SET_OPERAND_TYPE(3, OPERAND_SIZE_128_BIT); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_128_BIT); }
break;
case 83:
- { SET_OPERAND_TYPE(3, OPERAND_SIZE_256_BIT); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_256_BIT); }
break;
case 84:
- { SET_OPERAND_TYPE(3, OPERAND_FLOAT_SIZE_32_BIT); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_FLOAT_32_BIT); }
break;
case 85:
- { SET_OPERAND_TYPE(3, OPERAND_FLOAT_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_FLOAT_64_BIT); }
break;
case 86:
- { SET_OPERAND_TYPE(3, OPERAND_XMM); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_XMM); }
break;
case 87:
- { SET_OPERAND_TYPE(3, OPERAND_YMM); }
+ { SET_OPERAND_TYPE(3, OPERAND_TYPE_YMM); }
break;
case 88:
- { SET_OPERAND_TYPE(4, OPERAND_SIZE_2_BIT); }
+ { SET_OPERAND_TYPE(4, OPERAND_TYPE_2_BIT); }
break;
case 89:
{ SET_OPERAND_NAME(0, REG_DS_RBX); }
@@ -40176,13 +40129,13 @@
}
break;
case 123:
- { SET_OPERAND_TYPE(0, OPERAND_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(0, OPERAND_TYPE_64_BIT); }
break;
case 124:
- { SET_OPERAND_TYPE(1, OPERAND_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(1, OPERAND_TYPE_64_BIT); }
break;
case 125:
- { SET_OPERAND_TYPE(2, OPERAND_SIZE_64_BIT); }
+ { SET_OPERAND_TYPE(2, OPERAND_TYPE_64_BIT); }
break;
case 126:
{
@@ -44131,52 +44084,6 @@
break;
case 1411:
{
- switch (instruction.rm.disp_type) {
- case DISPNONE: instruction.rm.offset = 0; break;
- case DISP8: instruction.rm.offset = (int8_t) *disp; break;
- case DISP16: instruction.rm.offset =
- (uint16_t) (disp[0] + 256U * disp[1]);
- break;
- case DISP32: instruction.rm.offset = (int32_t)
- (disp[0] + 256U * (disp[1] + 256U * (disp[2] + 256U * (disp[3]))));
- break;
- case DISP64: instruction.rm.offset = (int64_t)
- (*disp + 256ULL * (disp[1] + 256ULL * (disp[2] + 256ULL * (disp[3] +
- 256ULL * (disp[4] + 256ULL * (disp[5] + 256ULL * (disp[6] + 256ULL *
- disp[7])))))));
- break;
- }
- switch (imm_operand) {
- case IMMNONE: instruction.imm[0] = 0; break;
- case IMM2: instruction.imm[0] = imm[0] & 0x03; break;
- case IMM8: instruction.imm[0] = imm[0]; break;
- case IMM16: instruction.imm[0] = (uint64_t) (*imm + 256U * (imm[1]));
- break;
- case IMM32: instruction.imm[0] = (uint64_t)
- (imm[0] + 256U * (imm[1] + 256U * (imm[2] + 256U * (imm[3]))));
- break;
- case IMM64: instruction.imm[0] = (uint64_t)
- (imm[0] + 256LL * (imm[1] + 256ULL * (imm[2] + 256ULL * (imm[3] +
- 256ULL * (imm[4] + 256ULL * (imm[5] + 256ULL * (imm[6] + 256ULL *
- imm[7])))))));
- break;
- }
- switch (imm2_operand) {
- case IMMNONE: instruction.imm[1] = 0; break;
- case IMM2: instruction.imm[1] = imm2[0] & 0x03; break;
- case IMM8: instruction.imm[1] = imm2[0]; break;
- case IMM16: instruction.imm[1] = (uint64_t)
- (imm2[0] + 256U * (imm2[1]));
- break;
- case IMM32: instruction.imm[1] = (uint64_t)
- (imm2[0] + 256U * (imm2[1] + 256U * (imm2[2] + 256U * (imm2[3]))));
- break;
- case IMM64: instruction.imm[1] = (uint64_t)
- (*imm2 + 256ULL * (imm2[1] + 256ULL * (imm2[2] + 256ULL * (imm2[3] +
- 256ULL * (imm2[4] + 256ULL * (imm2[5] + 256ULL * (imm2[6] + 256ULL *
- imm2[7])))))));
- break;
- }
process_instruction(instruction_start, current_position+1, &instruction,
userdata);
instruction_start = current_position + 1;
@@ -44190,6 +44097,7 @@
SET_REPZ_PREFIX(FALSE);
SET_BRANCH_NOT_TAKEN(FALSE);
SET_BRANCH_TAKEN(FALSE);
+ /* Top three bis of VEX2 are inverted: see AMD/Intel manual. */
SET_VEX_PREFIX2(0xe0);
SET_VEX_PREFIX3(0x00);
}
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