Move validator_x86_XX.rl out of unreviewed.

src/trusted/validator_ragel/gen/decoder_x86_32.c

Index: src/trusted/validator_ragel/gen/decoder_x86_32.c
===================================================================
--- src/trusted/validator_ragel/gen/decoder_x86_32.c	(revision 9911)
+++ src/trusted/validator_ragel/gen/decoder_x86_32.c	(working copy)
@@ -10,14 +10,23 @@
 #include <string.h>
 
 #include "native_client/src/shared/utils/types.h"
-#include "native_client/src/trusted/validator_ragel/unreviewed/decoding.h"
+#include "native_client/src/trusted/validator_ragel/decoder_internal.h"
 
 #include "native_client/src/trusted/validator_ragel/gen/decoder_x86_32_instruction_consts.h"
 
+/*
+ * These prefixes are not useful in IA32 mode, but they will “cleaned up” by
+ * decoder's cleanup procedure anyway.  Do nothing when that happens.
+ */
+#undef SET_REX_PREFIX
+#define SET_REX_PREFIX(P)
+#undef SET_VEX_PREFIX2
+#define SET_VEX_PREFIX2(P)
 
 
 
 
+
 static const short _x86_32_decoder_actions[] = {
 	0, 1, 0, 1, 1, 1, 2, 1, 
 	3, 1, 6, 1, 12, 1, 13, 1, 
@@ -9693,7 +9702,7 @@
 	87u, 88u, 95u, 96u, 103u, 104u, 111u, 112u, 
 	119u, 120u, 127u, 128u, 135u, 136u, 143u, 144u, 
 	151u, 152u, 159u, 160u, 167u, 168u, 175u, 176u, 
-	183u, 184u, 191u, 200u, 207u, 208u, 215u, 216u, 
+	183u, 184u, 191u, 192u, 199u, 208u, 215u, 216u, 
 	223u, 224u, 231u, 232u, 239u, 240u, 247u, 248u, 
 	255u, 4u, 5u, 12u, 13u, 20u, 21u, 28u, 
 	29u, 36u, 37u, 44u, 45u, 52u, 53u, 60u, 
@@ -9705,8 +9714,8 @@
 	95u, 96u, 103u, 104u, 111u, 112u, 119u, 120u, 
 	127u, 128u, 135u, 136u, 143u, 144u, 151u, 152u, 
 	159u, 160u, 167u, 168u, 175u, 176u, 183u, 184u, 
-	191u, 192u, 199u, 200u, 207u, 208u, 215u, 216u, 
-	223u, 224u, 231u, 232u, 239u, 248u, 255u, 4u, 
+	191u, 200u, 207u, 208u, 215u, 216u, 223u, 224u, 
+	231u, 232u, 239u, 240u, 247u, 248u, 255u, 4u, 
 	5u, 12u, 13u, 20u, 21u, 28u, 29u, 36u, 
 	37u, 44u, 45u, 52u, 53u, 60u, 61u, 68u, 
 	76u, 84u, 92u, 100u, 108u, 116u, 124u, 132u, 
@@ -12761,9 +12770,9 @@
 	80u, 87u, 88u, 95u, 96u, 103u, 104u, 111u, 
 	112u, 119u, 120u, 127u, 128u, 135u, 136u, 143u, 
 	144u, 151u, 152u, 159u, 160u, 167u, 168u, 175u, 
-	176u, 183u, 184u, 191u, 192u, 199u, 200u, 207u, 
-	208u, 215u, 216u, 223u, 224u, 231u, 232u, 239u, 
-	240u, 247u, 4u, 5u, 20u, 21u, 28u, 29u, 
+	176u, 183u, 184u, 191u, 200u, 207u, 208u, 215u, 
+	216u, 223u, 224u, 231u, 232u, 239u, 240u, 247u, 
+	248u, 255u, 4u, 5u, 20u, 21u, 28u, 29u, 
 	36u, 37u, 44u, 45u, 52u, 53u, 60u, 61u, 
 	68u, 84u, 92u, 100u, 108u, 116u, 124u, 132u, 
 	148u, 156u, 164u, 172u, 180u, 188u, 208u, 224u, 
@@ -15283,16 +15292,16 @@
 	3888, 3890, 3892, 3837, 3840, 3843, 3846, 3849, 
 	3852, 3855, 3858, 3861, 3863, 3865, 3867, 3869, 
 	3871, 3873, 3875, 3877, 3879, 3881, 3883, 3885, 
-	3887, 3889, 3891, 3894, 3895, 3896, 3897, 3898, 
-	3899, 3900, 3893, 3902, 3903, 3905, 3906, 3908, 
+	3887, 3889, 3891, 3893, 3895, 3896, 3897, 3898, 
+	3899, 3900, 3894, 3902, 3903, 3905, 3906, 3908, 
 	3909, 3911, 3912, 3914, 3915, 3917, 3918, 3920, 
 	3921, 3923, 3924, 3926, 3928, 3930, 3932, 3934, 
 	3936, 3938, 3940, 3942, 3944, 3946, 3948, 3950, 
 	3952, 3954, 3956, 3901, 3904, 3907, 3910, 3913, 
 	3916, 3919, 3922, 3925, 3927, 3929, 3931, 3933, 
 	3935, 3937, 3939, 3941, 3943, 3945, 3947, 3949, 
-	3951, 3953, 3955, 3957, 3958, 3959, 3960, 3961, 
-	3962, 3964, 3963, 3966, 3967, 3969, 3970, 3972, 
+	3951, 3953, 3955, 3958, 3959, 3960, 3961, 3962, 
+	3963, 3964, 3957, 3966, 3967, 3969, 3970, 3972, 
 	3973, 3975, 3976, 3978, 3979, 3981, 3982, 3984, 
 	3985, 3987, 3988, 3990, 3992, 3994, 3996, 3998, 
 	4000, 4002, 4004, 4006, 4008, 4010, 4012, 4014, 
@@ -18186,7 +18195,7 @@
 	10189, 10192, 10195, 10198, 10201, 10204, 10207, 10210, 
 	10213, 10215, 10217, 10219, 10221, 10223, 10225, 10227, 
 	10229, 10231, 10233, 10235, 10237, 10239, 10241, 10243, 
-	10245, 10246, 10247, 10248, 10249, 10250, 10251, 10252, 
+	10246, 10247, 10248, 10249, 10250, 10251, 10252, 10245, 
 	10254, 10255, 10257, 10258, 10260, 10261, 10263, 10264, 
 	10266, 10267, 10269, 10270, 10272, 10273, 10275, 10277, 
 	10279, 10281, 10283, 10285, 10287, 10289, 10291, 10293, 
@@ -21663,58 +21672,16 @@
 
 
 
-#define GET_VEX_PREFIX3() vex_prefix3
-#define SET_VEX_PREFIX3(P) vex_prefix3 = (P)
-#define SET_DATA16_PREFIX(S) instruction.prefix.data16 = (S)
-#define SET_LOCK_PREFIX(S) instruction.prefix.lock = (S)
-#define SET_REPZ_PREFIX(S) instruction.prefix.repz = (S)
-#define SET_REPNZ_PREFIX(S) instruction.prefix.repnz = (S)
-#define SET_BRANCH_TAKEN(S) instruction.prefix.branch_taken = (S)
-#define SET_BRANCH_NOT_TAKEN(S) instruction.prefix.branch_not_taken = (S)
-#define SET_INSTRUCTION_NAME(N) instruction.name = (N)
-#define GET_OPERAND_NAME(N) instruction.operands[(N)].name
-#define SET_OPERAND_NAME(N, S) instruction.operands[(N)].name = (S)
-#define SET_OPERAND_TYPE(N, S) instruction.operands[(N)].type = (S)
-#define SET_OPERANDS_COUNT(N) instruction.operands_count = (N)
-#define SET_MODRM_BASE(N) instruction.rm.base = (N)
-#define SET_MODRM_INDEX(N) instruction.rm.index = (N)
-#define SET_MODRM_SCALE(S) instruction.rm.scale = (S)
-#define SET_DISP_TYPE(T) instruction.rm.disp_type = (T)
-#define SET_DISP_PTR(P) disp = (P)
-#define SET_IMM_TYPE(T) imm_operand = (T)
-#define SET_IMM_PTR(P) imm = (P)
-#define SET_IMM2_TYPE(T) imm2_operand = (T)
-#define SET_IMM2_PTR(P) imm2 = (P)
-#define SET_CPU_FEATURE(F)
-
-enum {
-  REX_B = 1,
-  REX_X = 2,
-  REX_R = 4,
-  REX_W = 8
-};
-
-enum imm_mode {
-  IMMNONE,
-  IMM2,
-  IMM8,
-  IMM16,
-  IMM32
-};
-
 int DecodeChunkIA32(const uint8_t *data, size_t size,
-                    process_instruction_func process_instruction,
-                    process_decoding_error_func process_error, void *userdata) {
+                    ProcessInstructionFunc process_instruction,
+                    ProcessDecodingErrorFunc process_error, void *userdata) {
   const uint8_t *current_position = data;
   const uint8_t *end_of_data = data + size;
-  const uint8_t *disp = NULL;
-  const uint8_t *imm = NULL;
-  const uint8_t *imm2 = NULL;
   const uint8_t *instruction_start = current_position;
   uint8_t vex_prefix3 = 0x00;
-  enum imm_mode imm_operand = IMMNONE;
-  enum imm_mode imm2_operand = IMMNONE;
-  struct instruction instruction;
+  enum ImmediateMode imm_operand = IMMNONE;
+  enum ImmediateMode imm2_operand = IMMNONE;
+  struct Instruction instruction;
   int result = TRUE;
 
   int current_state;
@@ -21953,183 +21920,183 @@
 	{ SET_OPERANDS_COUNT(5); }
 	break;
 	case 27:
-	{ SET_OPERAND_TYPE(0, OPERAND_SIZE_16_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_16_BIT); }
 	break;
 	case 28:
-	{ SET_OPERAND_TYPE(0, OPERAND_SIZE_8_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_8_BIT); }
 	break;
 	case 29:
-	{ SET_OPERAND_TYPE(0, OPERAND_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_32_BIT); }
 	break;
 	case 30:
-	{ SET_OPERAND_TYPE(0, OPERAND_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_64_BIT); }
 	break;
 	case 31:
-	{ SET_OPERAND_TYPE(0, OPERAND_SIZE_128_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_128_BIT); }
 	break;
 	case 32:
-	{ SET_OPERAND_TYPE(0, OPERAND_SIZE_256_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_256_BIT); }
 	break;
 	case 33:
-	{ SET_OPERAND_TYPE(0, OPERAND_CONTROL_REGISTER); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_CONTROL_REGISTER); }
 	break;
 	case 34:
-	{ SET_OPERAND_TYPE(0, OPERAND_DEBUG_REGISTER); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_DEBUG_REGISTER); }
 	break;
 	case 35:
-	{ SET_OPERAND_TYPE(0, OPERAND_FAR_PTR); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_FAR_PTR); }
 	break;
 	case 36:
-	{ SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_32_BIT); }
 	break;
 	case 37:
-	{ SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_64_BIT); }
 	break;
 	case 38:
-	{ SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_80_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_80_BIT); }
 	break;
 	case 39:
-	{ SET_OPERAND_TYPE(0, OPERAND_MMX); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_MMX); }
 	break;
 	case 40:
-	{ SET_OPERAND_TYPE(0, OPERAND_SEGMENT_REGISTER); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_SEGMENT_REGISTER); }
 	break;
 	case 41:
-	{ SET_OPERAND_TYPE(0, OPERAND_SELECTOR); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_SELECTOR); }
 	break;
 	case 42:
-	{ SET_OPERAND_TYPE(0, OPERAND_ST); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_ST); }
 	break;
 	case 43:
-	{ SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_16_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_16_BIT); }
 	break;
 	case 44:
-	{ SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_32_BIT); }
 	break;
 	case 45:
-	{ SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_64_BIT); }
 	break;
 	case 46:
-	{ SET_OPERAND_TYPE(0, OPERAND_X87_BCD); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_BCD); }
 	break;
 	case 47:
-	{ SET_OPERAND_TYPE(0, OPERAND_X87_ENV); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_ENV); }
 	break;
 	case 48:
 	{
-    SET_OPERAND_TYPE(0, OPERAND_X87_MMX_MM_STATE);
+    SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_MMX_XMM_STATE);
   }
 	break;
 	case 49:
-	{ SET_OPERAND_TYPE(0, OPERAND_X87_STATE); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_STATE); }
 	break;
 	case 50:
-	{ SET_OPERAND_TYPE(0, OPERAND_XMM); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_XMM); }
 	break;
 	case 51:
-	{ SET_OPERAND_TYPE(0, OPERAND_YMM); }
+	{ SET_OPERAND_TYPE(0, OPERAND_TYPE_YMM); }
 	break;
 	case 52:
-	{ SET_OPERAND_TYPE(1, OPERAND_SIZE_8_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_8_BIT); }
 	break;
 	case 53:
-	{ SET_OPERAND_TYPE(1, OPERAND_SIZE_16_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_16_BIT); }
 	break;
 	case 54:
-	{ SET_OPERAND_TYPE(1, OPERAND_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_32_BIT); }
 	break;
 	case 55:
-	{ SET_OPERAND_TYPE(1, OPERAND_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_64_BIT); }
 	break;
 	case 56:
-	{ SET_OPERAND_TYPE(1, OPERAND_SIZE_128_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_128_BIT); }
 	break;
 	case 57:
-	{ SET_OPERAND_TYPE(1, OPERAND_SIZE_256_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_256_BIT); }
 	break;
 	case 58:
-	{ SET_OPERAND_TYPE(1, OPERAND_CONTROL_REGISTER); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_CONTROL_REGISTER); }
 	break;
 	case 59:
-	{ SET_OPERAND_TYPE(1, OPERAND_DEBUG_REGISTER); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_DEBUG_REGISTER); }
 	break;
 	case 60:
-	{ SET_OPERAND_TYPE(1, OPERAND_FAR_PTR); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_FAR_PTR); }
 	break;
 	case 61:
-	{ SET_OPERAND_TYPE(1, OPERAND_FLOAT_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_FLOAT_32_BIT); }
 	break;
 	case 62:
-	{ SET_OPERAND_TYPE(1, OPERAND_FLOAT_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_FLOAT_64_BIT); }
 	break;
 	case 63:
-	{ SET_OPERAND_TYPE(1, OPERAND_MMX); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_MMX); }
 	break;
 	case 64:
-	{ SET_OPERAND_TYPE(1, OPERAND_SEGMENT_REGISTER); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_SEGMENT_REGISTER); }
 	break;
 	case 65:
-	{ SET_OPERAND_TYPE(1, OPERAND_ST); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_ST); }
 	break;
 	case 66:
-	{ SET_OPERAND_TYPE(1, OPERAND_XMM); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_XMM); }
 	break;
 	case 67:
-	{ SET_OPERAND_TYPE(1, OPERAND_YMM); }
+	{ SET_OPERAND_TYPE(1, OPERAND_TYPE_YMM); }
 	break;
 	case 68:
-	{ SET_OPERAND_TYPE(2, OPERAND_SIZE_8_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_8_BIT); }
 	break;
 	case 69:
-	{ SET_OPERAND_TYPE(2, OPERAND_SIZE_16_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_16_BIT); }
 	break;
 	case 70:
-	{ SET_OPERAND_TYPE(2, OPERAND_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_32_BIT); }
 	break;
 	case 71:
-	{ SET_OPERAND_TYPE(2, OPERAND_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_64_BIT); }
 	break;
 	case 72:
-	{ SET_OPERAND_TYPE(2, OPERAND_SIZE_128_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_128_BIT); }
 	break;
 	case 73:
-	{ SET_OPERAND_TYPE(2, OPERAND_SIZE_256_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_256_BIT); }
 	break;
 	case 74:
-	{ SET_OPERAND_TYPE(2, OPERAND_FLOAT_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_FLOAT_32_BIT); }
 	break;
 	case 75:
-	{ SET_OPERAND_TYPE(2, OPERAND_FLOAT_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_FLOAT_64_BIT); }
 	break;
 	case 76:
-	{ SET_OPERAND_TYPE(2, OPERAND_XMM); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_XMM); }
 	break;
 	case 77:
-	{ SET_OPERAND_TYPE(2, OPERAND_YMM); }
+	{ SET_OPERAND_TYPE(2, OPERAND_TYPE_YMM); }
 	break;
 	case 78:
-	{ SET_OPERAND_TYPE(3, OPERAND_SIZE_8_BIT); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_8_BIT); }
 	break;
 	case 79:
-	{ SET_OPERAND_TYPE(3, OPERAND_SIZE_128_BIT); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_128_BIT); }
 	break;
 	case 80:
-	{ SET_OPERAND_TYPE(3, OPERAND_SIZE_256_BIT); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_256_BIT); }
 	break;
 	case 81:
-	{ SET_OPERAND_TYPE(3, OPERAND_FLOAT_SIZE_32_BIT); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_FLOAT_32_BIT); }
 	break;
 	case 82:
-	{ SET_OPERAND_TYPE(3, OPERAND_FLOAT_SIZE_64_BIT); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_FLOAT_64_BIT); }
 	break;
 	case 83:
-	{ SET_OPERAND_TYPE(3, OPERAND_XMM); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_XMM); }
 	break;
 	case 84:
-	{ SET_OPERAND_TYPE(3, OPERAND_YMM); }
+	{ SET_OPERAND_TYPE(3, OPERAND_TYPE_YMM); }
 	break;
 	case 85:
-	{ SET_OPERAND_TYPE(4, OPERAND_SIZE_2_BIT); }
+	{ SET_OPERAND_TYPE(4, OPERAND_TYPE_2_BIT); }
 	break;
 	case 86:
 	{ SET_OPERAND_NAME(0, REG_DS_RBX); }
@@ -22246,13 +22213,13 @@
   }
 	break;
 	case 120:
-	{  SET_OPERAND_TYPE(0, OPERAND_SIZE_32_BIT); }
+	{  SET_OPERAND_TYPE(0, OPERAND_TYPE_32_BIT); }
 	break;
 	case 121:
-	{  SET_OPERAND_TYPE(1, OPERAND_SIZE_32_BIT); }
+	{  SET_OPERAND_TYPE(1, OPERAND_TYPE_32_BIT); }
 	break;
 	case 122:
-	{  SET_OPERAND_TYPE(2, OPERAND_SIZE_32_BIT); }
+	{  SET_OPERAND_TYPE(2, OPERAND_TYPE_32_BIT); }
 	break;
 	case 123:
 	{
@@ -26101,50 +26068,21 @@
 	break;
 	case 1381:
 	{
-        switch (instruction.rm.disp_type) {
-          case DISPNONE: instruction.rm.offset = 0; break;
-          case DISP8: instruction.rm.offset = (int8_t) *disp; break;
-          case DISP16: instruction.rm.offset =
-            (int16_t) (disp[0] + 256U * disp[1]);
-            break;
-          case DISP32: instruction.rm.offset = (int32_t)
-            (disp[0] + 256U * (disp[1] + 256U * (disp[2] + 256U * (disp[3]))));
-            break;
-          case DISP64: assert(FALSE);
-        }
-        switch (imm_operand) {
-          case IMMNONE: instruction.imm[0] = 0; break;
-          case IMM2: instruction.imm[0] = imm[0] & 0x03; break;
-          case IMM8: instruction.imm[0] = imm[0]; break;
-          case IMM16: instruction.imm[0] = (uint64_t) (*imm + 256U * (imm[1]));
-            break;
-          case IMM32: instruction.imm[0] = (uint64_t)
-            (imm[0] + 256U * (imm[1] + 256U * (imm[2] + 256U * (imm[3]))));
-            break;
-        }
-        switch (imm2_operand) {
-          case IMMNONE: instruction.imm[1] = 0; break;
-          case IMM2: instruction.imm[1] = imm2[0] & 0x03; break;
-          case IMM8: instruction.imm[1] = imm2[0]; break;
-          case IMM16: instruction.imm[1] = (uint64_t)
-            (imm2[0] + 256U * (imm2[1]));
-            break;
-          case IMM32: instruction.imm[1] = (uint64_t)
-            (imm2[0] + 256U * (imm2[1] + 256U * (imm2[2] + 256U * (imm2[3]))));
-            break;
-        }
         process_instruction(instruction_start, current_position+1, &instruction,
                             userdata);
         instruction_start = current_position + 1;
         SET_DISP_TYPE(DISPNONE);
         SET_IMM_TYPE(IMMNONE);
         SET_IMM2_TYPE(IMMNONE);
+        SET_REX_PREFIX(FALSE);
         SET_DATA16_PREFIX(FALSE);
         SET_LOCK_PREFIX(FALSE);
         SET_REPNZ_PREFIX(FALSE);
         SET_REPZ_PREFIX(FALSE);
         SET_BRANCH_NOT_TAKEN(FALSE);
         SET_BRANCH_TAKEN(FALSE);
+        /* Top three bis of VEX2 are inverted: see AMD/Intel manual.  */
+        SET_VEX_PREFIX2(0xe0);
         SET_VEX_PREFIX3(0x00);
     }
 	break;