Index: src/compiler/pipeline.cc |
diff --git a/src/compiler/pipeline.cc b/src/compiler/pipeline.cc |
index 0d28dafb708d5f50121a4c8ee14c216c912218f4..59684c1ac10d2fca9bc7ae65b2a77d72cbcba910 100644 |
--- a/src/compiler/pipeline.cc |
+++ b/src/compiler/pipeline.cc |
@@ -742,25 +742,23 @@ |
}; |
-template <typename RegAllocator> |
struct AllocateGeneralRegistersPhase { |
static const char* phase_name() { return "allocate general registers"; } |
void Run(PipelineData* data, Zone* temp_zone) { |
- RegAllocator allocator(data->register_allocation_data(), GENERAL_REGISTERS, |
- temp_zone); |
+ LinearScanAllocator allocator(data->register_allocation_data(), |
+ GENERAL_REGISTERS, temp_zone); |
allocator.AllocateRegisters(); |
} |
}; |
-template <typename RegAllocator> |
struct AllocateDoubleRegistersPhase { |
static const char* phase_name() { return "allocate double registers"; } |
void Run(PipelineData* data, Zone* temp_zone) { |
- RegAllocator allocator(data->register_allocation_data(), DOUBLE_REGISTERS, |
- temp_zone); |
+ LinearScanAllocator allocator(data->register_allocation_data(), |
+ DOUBLE_REGISTERS, temp_zone); |
allocator.AllocateRegisters(); |
} |
}; |
@@ -1271,13 +1269,8 @@ |
if (verifier != nullptr) { |
CHECK(!data->register_allocation_data()->ExistsUseWithoutDefinition()); |
} |
- if (FLAG_turbo_greedy_regalloc) { |
- Run<AllocateGeneralRegistersPhase<GreedyAllocator>>(); |
- Run<AllocateDoubleRegistersPhase<GreedyAllocator>>(); |
- } else { |
- Run<AllocateGeneralRegistersPhase<LinearScanAllocator>>(); |
- Run<AllocateDoubleRegistersPhase<LinearScanAllocator>>(); |
- } |
+ Run<AllocateGeneralRegistersPhase>(); |
+ Run<AllocateDoubleRegistersPhase>(); |
Run<AssignSpillSlotsPhase>(); |
Run<CommitAssignmentPhase>(); |