ARM64: Support sign extend for add and subtract

src/compiler/arm64/instruction-codes-arm64.h

Index: src/compiler/arm64/instruction-codes-arm64.h
diff --git a/src/compiler/arm64/instruction-codes-arm64.h b/src/compiler/arm64/instruction-codes-arm64.h
index be0981f652d6a80fdb0897b1fbba7e6a8114a8e7..2d473ad1f7c1905f1a1a938f0e4a592599cc39a4 100644
--- a/src/compiler/arm64/instruction-codes-arm64.h
+++ b/src/compiler/arm64/instruction-codes-arm64.h
@@ -141,15 +141,17 @@ namespace compiler {
 // I = immediate (handle, external, int32)
 // MRI = [register + immediate]
 // MRR = [register + register]
-#define TARGET_ADDRESSING_MODE_LIST(V)                      \
-  V(MRI)              /* [%r0 + K] */                       \
-  V(MRR)              /* [%r0 + %r1] */                     \
-  V(Operand2_R_LSL_I) /* %r0 LSL K */                       \
-  V(Operand2_R_LSR_I) /* %r0 LSR K */                       \
-  V(Operand2_R_ASR_I) /* %r0 ASR K */                       \
-  V(Operand2_R_ROR_I) /* %r0 ROR K */                       \
-  V(Operand2_R_UXTB)  /* %r0 UXTB (unsigned extend byte) */ \
-  V(Operand2_R_UXTH)  /* %r0 UXTH (unsigned extend halfword) */
+#define TARGET_ADDRESSING_MODE_LIST(V)                          \
+  V(MRI)              /* [%r0 + K] */                           \
+  V(MRR)              /* [%r0 + %r1] */                         \
+  V(Operand2_R_LSL_I) /* %r0 LSL K */                           \
+  V(Operand2_R_LSR_I) /* %r0 LSR K */                           \
+  V(Operand2_R_ASR_I) /* %r0 ASR K */                           \
+  V(Operand2_R_ROR_I) /* %r0 ROR K */                           \
+  V(Operand2_R_UXTB)  /* %r0 UXTB (unsigned extend byte) */     \
+  V(Operand2_R_UXTH)  /* %r0 UXTH (unsigned extend halfword) */ \
+  V(Operand2_R_SXTB)  /* %r0 SXTB (signed extend byte) */       \
+  V(Operand2_R_SXTH)  /* %r0 SXTH (signed extend halfword) */
 
 }  // namespace internal
 }  // namespace compiler